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smsc com20022i page 1 rev. 08-18-03 datasheet com20022i 10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet product features new features ? data rates up to 10 mbps ? selectable 8/16 bit wide bus with data swapper ? programmable dma channel ? programmable reconfiguration times ? 48 pin tqfp package ideal for industrial/factory/building automation and transportation applications deterministic, (ansi 878.1), token passing arcnet protocol minimal microcontroller and media interface logic required flexible interface for use with all microcontrollers or microprocessors automatically detects ty pe of microcontroller interface 2kx8 on-chip dual port ram command chaining for packet queuing sequential access to internal ram software programmable node id eight, 256 byte pages allow four pages tx and rx plus scratch-pad memory next id readable internal clock scaler and clock multiplier for adjusting network speed operating temperature range of -40 o c to +85 o c self-reconfiguration protocol supports up to 255 nodes supports various network topologies (star, tree, bus...) cmos, single +5v supply duplicate node id detection powerful diagnostics receive all packets mode flexible media interface: ? traditional hybrid interf ace for long distances up to four miles at 2.5mbps ? rs485 differential driver interface for low cost, low power, high reliability
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 2 smsc com20022i datasheet ordering information order number(s): COM20022ITQFP for 48 pin tqfp package 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? smsc 2004. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for c onstruction purposes is not necessarily given. although the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent ri ghts or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (t he "terms of sale agreement"). the product may contain design def ects or errors known as anomalies which may caus e the product's functions to deviate from publis hed specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where produc t failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at t he risk of the customer. copies of this do cument or other smsc literature, as wel l as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www .smsc.com. smsc is a registered trademark of standard micros ystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitn ess for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for an y direct, incidental , indirect, special, punitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of th e form of action, whether based on contract; tort; negligence of smsc or others; strict li ability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whet her or not smsc has been advised of the possibility of such damages.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 3 rev. 08-18-03 datasheet revision history revision level and date section/figure/entry correction 2/25/99 section 7.1 - maximum guaranteed ratings*, pg. 57 updated section. 6/8/99 figure 9.1 - com20022i 48 pin tqfp package outline and table 9.1 - com20022i 48 pin tqfp package parameters, pg. 79 updated figure and table.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 4 smsc com20022i datasheet table of contents revision history ............................................................................................................... ........................... 3 chapter 1 general de scription............................................................................................................ .... 7 chapter 2 pin config uration.............................................................................................................. ...... 8 chapter 3 description of pi n functions .................................................................................................. 9 chapter 4 protocol de scription ........................................................................................................... .. 12 4.1 network pr otocol ............................................................................................................... .........................12 4.2 data ra tes ..................................................................................................................... ............................12 4.2.1 selecting clock frequencie s above 2. 5 mbps....................................................................................1 3 4.3 network reconf igurat ion ........................................................................................................ ....................13 4.4 broadcast mess ages ............................................................................................................. .....................14 4.5 extended timeout func tion ...................................................................................................... .................14 4.5.1 response time .................................................................................................................. .................14 4.5.2 idle time ...................................................................................................................... .......................14 4.5.3 reconfigurat ion time ........................................................................................................... ...............14 4.6 line pr otocol .................................................................................................................. ............................15 4.6.1 invitations to trans mit........................................................................................................ ................15 4.6.2 free buffer enquiri es .......................................................................................................... ................15 4.6.3 data pa ckets................................................................................................................... ....................15 4.6.4 acknowledg ements ............................................................................................................... ..............16 4.6.5 negative ackn owledgements ...................................................................................................... ........16 chapter 5 system desc ription ............................................................................................................. .17 5.1 microcontroller interf ace...................................................................................................... .......................17 5.1.1 selection of 8/ 16-bit a ccess ................................................................................................... ............20 5.1.2 dma transfers to and fr om internal ram ........................................................................................2 0 5.1.3 dma oper ation .................................................................................................................. .................21 5.1.4 dma data transfer sequence (i/o to memory: read a packet ) ........................................................25 5.1.5 dma data transfer sequence (memo ry to i/o: writ e a packe t).........................................................25 5.1.6 high speed cpu bus timing suppor t .............................................................................................. ..25 5.2 transmission medi a interf ace ................................................................................................... .................26 5.2.1 traditional hybr id inte rface ................................................................................................... ..............27 5.2.2 backplane conf igurat ion ........................................................................................................ .............27 5.2.3 differential driver configur ation .............................................................................................. ............29 5.2.4 programmable t xen pola rity ..................................................................................................... ........29 chapter 6 functional de scription......................................................................................................... .31 6.1 microseq uencer................................................................................................................. .........................31 6.2 internal r egister s ............................................................................................................. ..........................33 6.2.1 interrupt mask r egister (imr) .................................................................................................. ...........33 6.2.2 data re gist er .................................................................................................................. ....................34 6.2.3 tentative id regi ster .......................................................................................................... ................34 6.2.4 node id regist er............................................................................................................... ..................34 6.2.5 next id regist er............................................................................................................... ...................35 6.2.6 status r egister................................................................................................................ ....................35 6.2.7 diagnostic stat us regi ster..................................................................................................... .............35 6.2.8 command r egister ............................................................................................................... ..............35 6.2.9 address pointe r regist ers ...................................................................................................... ............35 6.2.10 configurati on regi ster......................................................................................................... ............36 6.2.11 sub-address regist er ........................................................................................................... ..........36 6.2.12 setup 1 re gist er............................................................................................................... ...............36 6.2.13 setup 2 re gist er............................................................................................................... ...............36 6.3 bus control regist er ........................................................................................................... .......................37 6.4 dma count regist er ............................................................................................................. .....................37 6.5 internal ram ................................................................................................................... ...........................48 6.5.1 sequential ac cess me mory....................................................................................................... ..........48 6.5.2 access s peed ................................................................................................................... ..................48 6.6 software in terface ............................................................................................................. .........................48 6.6.1 selecting ra m page size ........................................................................................................ ...........49 6.6.2 transmit s equenc e .............................................................................................................. ...............50
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 5 rev. 08-18-03 datasheet 6.6.3 receive se quence ............................................................................................................... ...............51 6.7 command c haining............................................................................................................... .....................52 6.7.1 transmit comma nd chai ning ...................................................................................................... .......52 6.7.2 receive comma nd chai ning ....................................................................................................... .......53 6.8 reset de tails.................................................................................................................. ............................54 6.8.1 internal re set log ic ........................................................................................................... .................54 6.9 initializatio n seque nce ........................................................................................................ .......................54 6.9.1 bus determ ination.............................................................................................................. .................54 6.10 improved di agnosti cs ........................................................................................................... ..................55 6.10.1 normal re sults: ................................................................................................................ ...............55 6.10.2 abnormal re sults: .............................................................................................................. .............56 6.11 oscilla tor..................................................................................................................... ............................56 chapter 7 operational de script ion........................................................................................................ 57 7.1 maximum guarant eed rati ngs* .................................................................................................... .............57 7.2 dc electrical c haracteri stics.................................................................................................. ....................57 chapter 8 timing di agrams ................................................................................................................ .. 60 chapter 9 package ou tline ................................................................................................................ ... 79 chapter 10 appendix a ..................................................................................................................... ...... 80 10.1 nosync bit ..................................................................................................................... ......................80 10.2 ef bit......................................................................................................................... .............................80 chapter 11 appendix b: example of interface circuit diagram to isa bus........................................... 83 list of figures figure 2.1 - com20022i pin confi guration ....................................................................................... .............................8 figure 3.1 - com20022i operation ..........................................................................................................................11 figure 5.1 - multiplexed, 8051-like bus interface with rs-485 interface ............................................................18 figure 5.2 - non-multiplexed, 6801-like bus interface with rs-485 interface ....................................................19 figure 5.3 - dreq pin first asse rtion timing for all dma modes ................................................................. ..............22 figure 5.4 - programmable burst mode dma transfer (rough timing) ............................................................23 figure 5.5 - non-burst mode dma data transfer rough ti ming..................................................................... ............24 figure 5.6 - burst mode dma data transfer rough timing ................................................................................24 figure 5.7 - high speed cpu bus timing - intel cpu mode ...............................................................................26 figure 5.8 - com20022i network using rs-485 differential transceivers .........................................................28 figure 5.9 - dipulse waveform for data of 1-1-0 ....................................................................................................28 figure 5.10 - internal block diagram ........................................................................................................................29 figure 6.1 - illustration of the effect of rtrg bit on dma timing ......................................................................37 figure 6.2 - sequential access operation ...............................................................................................................47 figure 6.3 - ram buffer packet config uration ................................................................................... ..........................50 figure 6.4 - command chaining status register queue ............................................................................ .................52 figure 8.1 - multiplexed bus, 68xx-like control signals; read cycle ..............................................................60 figure 8.2 - multiplexed bus, 80xx-like control signals; read cycle ..............................................................61 figure 8.3 - multiplexed bus, 68xx-like control signals write cycle ...............................................................62 figure 8.4 - multiplexed bus, 80xx-like control signals; write cycle ..............................................................63 figure 8.5 - non-multiplexed bus, 80xx-like control signals; read cycle .....................................................64 figure 8.6 - non-multiplexed bus, 80xx-like control signals; read cycle .....................................................65 figure 8.7 - non-multiplexed bus, 68xx-like control signals; read cycle .....................................................66 figure 8.8 - non-multiplexed bus, 68xx-like control signals; read cycle .....................................................67 figure 8.9 - non-multiplex ed bus, 80xx-like control signals; write cycle....................................................... ..........68 figure 8.10 - non-multiplexed bus, 80xx -like control signal s; write cycle ...................................................... .........69 figure 8.11 - non-multiplexed bus, 68xx-like control signals; write cycle ....................................................70 figure 8.12 - non-multiplexed bus, 68xx -like control signal s; write cycle ...................................................... .........71 figure 8.13 - normal mode tr ansmit or rece ive ti ming........................................................................... ...................72 figure 8.14 - backplane mode transmit or re ceive ti ming ........................................................................ ................73 figure 8.15 - ttl input timing on xtal1 pin ........................................................................................................74 figure 8.16 - reset and interrupt timing ................................................................................................................74
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 6 smsc com20022i datasheet figure 8.17 - dma timing (intel mode 80xx) ........................................................................................................75 figure 8.18 - dma timing (motorola mode 68xx) ................................................................................................76 figure 9.1 - com20022i 48 pi n tqfp pack age outl ine............................................................................. .................79 figure 10.1 - effect of the ef bit on the ta/ri bit .................................................................................................82 list of tables table 5.1 - ty pical media ...................................................................................................... .......................................30 table 6.1 - read re gister summary.............................................................................................. ..............................32 table 6.2 - write register summary ............................................................................................. ...............................33 table 6.3 - stat us register .................................................................................................... .......................................38 table 6.4 - diagnosti c status register......................................................................................... .................................39 table 6.5 - comm and register................................................................................................... ..................................40 table 6.6 - address po inter high register ...................................................................................... ..............................41 table 6.7 - address po inter low register....................................................................................... ..............................42 table 6.8 - sub ad dress register ............................................................................................... ..................................42 table 6.9 - config uration register ............................................................................................. ...................................43 table 6.10 - setu p 1 register .................................................................................................. .....................................44 table 6.11 - setu p 2 register .................................................................................................. .....................................45 table 6.12 - bus c ontrol register.............................................................................................. ...................................46 table 6.13 - dma count register................................................................................................ .................................47 table 8.1 - dma timing......................................................................................................... .......................................77 table 9.1 - com20022i 48 pi n tqfp package parame ters........................................................................... .............79 for more details on the arcnet protocol engine and traditional dipulse signaling schemes, please refer to the arcnet local area network standard , or the arcnet designer's handbook , available from datapoint corporation.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 7 rev. 08-18-03 datasheet chapter 1 general description smsc's com20022i is a member of the fami ly of embedded arcnet controllers from standard microsystems corporation. the device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in indus trial, automotive, and embedded control environments using an arcnet protocol engine. the small 48 pin package, flexible microcontroller and media interfaces, eight- page message support, and extended temperature range of t he com20022i make it the only true network controller optimized for use in industr ial, embedded, and automotive applications. using an arcnet protocol engine is the ideal solution for em bedded control applications because it provides a deterministic token-passing protocol, a highly reliabl e and proven networking scheme, and a data rate of up to 10 mbps when using the com20022i. a token-passing protocol provides predictable response times because each network event occurs within a predetermined time interval, based upon the number of nodes on the network. the deterministic nature of a rcnet is essential in real time applications. the integration of the 2kx8 ram buffer on-chip, the command chaining feat ure, the 10 mbps maximum data rate, and the internal diagnostics make the com20022i the highest pe rformance embedded communications device available. with only one co m20022i and one microcontroller, a complete communications node may be implemented.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 8 smsc com20022i datasheet chapter 2 pin configuration com20022 48 pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 ad0 ad1 d10 ad2 d11 d3 vdd d4 d5 vss d6 vss 13 14 15 16 17 18 19 20 21 22 23 24 d7 d12 d13 d14 d15 n/c vdd xtal1 xtal2 npulse1 vss vss 25 36 35 34 33 32 31 30 29 28 27 26 npulse2 bustmg n/c rxin ntxen nreset vdd dreq nintr ndack ncs vss 37 38 39 40 41 42 43 44 45 46 47 48 tc d9 d8 a2/ale a1 a0/nmux vdd niocs16 nrefex nrd/nds nwr/dir vss ordering information: package type: tqfp temp range: (blank) = commercial: 0c to +70c i = industrial: -40c to +85c device type: 20022 = universal local area network controller (with 2k x 8 ram) com20022 figure 2.1 - com20022i pin configuration com20022i 48 pin tqfp ordering information: com20022i package type: tqfp temp range: (blank) = commercial 0 c to + 70 1 = industrial: -40 c to +85 c device type: 20022i = universal local area network controller (with 2k x 8 ram)
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 9 rev. 08-18-03 datasheet chapter 3 description of pin functions pin no name symbol i/o description microcontroller interface 44,45, 46 address 0-2 a0/nmux a1 a2/ale in in in on a non-multiplexed mode, a0-a2 are address input bits. (a0 is the lsb) on a multiplexed address/data bus, nmux tied low, a1 is left open, and ale is tied to the address latch enable signal. a1 is connected to an internal pull-up resistor. 1,2,4, 7,9, 10,12, 13 data 0-7 ad0-ad2, d3-d7 i/o on a non-multiplexed bus, these signals are used as the lower byte data bus lines. on a multiplexed address/data bus, ad0-ad2 act as the address lines (latched by ale) and as the low data lines. d3-d7 are always used for data only. these signals are connected to internal pull-up resistors. 47, 48, 3,5, 14-17 data 8-15 d8-d15 i/o d8-d15 are always used as the higher byte data bus lines only for 16bit internal ram access. when the 16bit access is disabled, these signals are always hi-z. enabling or disabling the 16bit access is programmable. a data swapper is built in. these signals are connected to internal pull-up resistors. 37 nwrite/ direction nwr/dir in nwr is for 80xx cpu, nwr is write signal input. active low. dir is for 68xx cpu, dir is bus direction signal input. (low: write, high: read.) 39 nread/ ndata strobe nrd/nds in nrd is for 80xx cpu, nrd is read signal input. active low. nds is for 68xx cpu, nds is data strobe signal input. active low. 31 nreset in nreset in hardware reset signal. active low. 34 ninterrupt nintr out interrupt signal output. active low. 36 nchip select ncs in chip select input. active low. 42 ni/o 16 bit indicator niocs16 out this signal is an active low signal which indicates accessing 16bit data only by cpu. this signal becomes active when cpu accesses to data register only if w16 bit is 1. this signal is same as on isa bus signal, but it?s not open-drain. an external open-drain buffer is needed when this signal connects to the isa bus. 26 read/write bus timing select bustmg in read and write bus access timing mode selecting signal. status of this signal effects cpu and dma timing. l: high speed timing mode (only for non-multiplexed bus) h: normal timing mode this signal is connected to internal pull-up registers. 33 dma request dreq out dma request signal. active polarity is programmable. default is active high. 35 dma ack ndack in dma acknowledge signal. active low. when bustmg is high, this signal is connected to internal pull-up registers 38 terminal count tc in terminal count signal. active polarity is programmable. default is active high. when bu stmg is high, this signal is connected to the internal pull-up resistor. 40 refresh execution nrefex in refresh execution signal. falling edge detection. this signal is connected to the internal pull-up resistor.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 10 smsc com20022i datasheet pin no name symbol i/o description transmission media interface 24 25 npulse 1 npulse 2 npulse1 npulse2 out i/o in normal mode, these active low signals carry the transmit data information, encoded in pulse format as dipulse waveform. in backplane mode, the npulse1 signal driver is programmable (push/pull or open-drain), while the npulse2 signal provides a clock with frequency of doubled data rate. npulse1 is connected to a weak internal pull-up resistor on the open/drain dr iver in backplane mode. 28 receive in rxin in this signal carries the receive data information from the line transceiver. 29 ntransmit enable ntxen out transmission enable signal. active polarity is programmable through the npulse2 pin. npulse2 floating before power-up; ntxen active low npulse2 grounded before power-up; ntxen active high (this option is only available in back plane mode) 21 22 crystal oscillator xtal1 xtal2 in out an external crystal should be connected to these pins. oscillation frequency range is from 10 mhz to 20 mhz. if an external ttl clock is used instead, it must be connected to xtal1 with a 390ohm pull-up resistor, and xtal2 should be left floating. 8,20, 32,43 power supply vdd pwr +5 volt power supply pins. 6,11, 18,23, 30,41 ground vss pwr ground pins. 19,27 n/c n/c non-connection
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 11 rev. 08-18-03 datasheet invitation to transmit to this id? y n free buffer enquiry to this id? soh? yn yn ri? write sid to buffer did =0? did =id? write buffer with packet crc ok? length ok? did =0? did =id? send ack n y n y n y n broadcast enabled? n y n no activity for 20.5 us? y n set nid=id start timer: t=(255-id) activity on line? y n t=0? set ri ri? tr a n s m i t nak tr a n s m i t ack set nid=id write id to ram buffer send reconfigure burst power on reconfigure timer has timed out start reconfiguration timer (210 ms)* ta ? broadcast? tr a n s m i t free buffer enquiry no activity pass the to k e n set ta y n ack? nak? 1 no activity n y increment nid send packet was packet broadcast? no activity n ack? set tma set ta x 36.5 us for 18.7 us? for 18.7 us? for 18.7 us? y n n y y n n y n n n n 1 y y y y y y y n y read node id id refers to the identification number of the id assigned to this node. nid refers to the next identification number that receives the token after this id passes it. - - - - sid refers to the source identification. did refers to the destination identification. soh refers to the start of header character; preceeds all data packets. - yn * reconfig timer is programmable via setup2 register bits 1, 0. note - all time values are valid for 10mbps. figure 3.1 - com20022i operation
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 12 smsc com20022i datasheet chapter 4 protocol description 4.1 network protocol communication on the network is based on a token pa ssing protocol. establishment of the network configuration and management of t he network protocol are handled entir ely by the com20022i's internal microcoded sequencer. a processor or intelligent peripher al transmits data by simply loading a data packet and its destination id into the com20022i's intern al ram buffer, and issuing a command to enable the transmitter. when the com20022i next receives the token, it verifies t hat the receiving node is ready by first transmitting a free buffer enquiry message. if the receiving node transmits an acknowledge message, the data packet is transmitted followed by a 16- bit crc. if the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a negative acknowledge message and the transmitter passes the token. once it has been estab lished that the receiving node can accept the packet and transmission is complete, the receiving node ve rifies the packet. if the packet is received successfully, the receiving node transmits an acknowledge message (or nothing if it is not received successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. an interrupt mask permits the com20022i to generate an interrupt to the processor when selected status bits become true. figure 2.1 is a flow chart illustrating the internal operation of the com20022i connected to a 20 mhz crystal oscillator. 4.2 data rates the com20022i is capable of supporting data rates from 156.25 kbps to 10 mbps. the following protocol description assumes a 10 mbps data rate. to attain the faster data rates, the clock frequency may be doubled or quadrupled by the internal clock multiplier (see next section). for slower data rates, an internal clock divider scales down the clock frequency. thus all timeout values are scaled as shown in the following table: example: idle line timeout @ 10 mbps = 20.5 s. idle line timeout for 156.2 kbps is 20.5 s * 64 = 1.3 ms internal clock frequency clock prescaler data rate timeout scaling factor (multiply by) 80 mhz div. by 8 10 mbps 1 40 mhz div. by 8 5 mbps 2 20 mhz div. by 8 div. by 16 div. by 32 div. by 64 div. by 128 2.5 mbps 1.25 mbps 625 kbps 312.5 kbps 156.25 kbps 4 8 16 32 64
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 13 rev. 08-18-03 datasheet 4.2.1 selecting clock fre quencies above 2.5 mbps to realize a 10 mbps network, an external 80 mhz clock must be input. however, since 80 mhz is the frequency of fm radio band, it is not practical for use for noise emission reasons. therefore, higher frequency clocks are generated from the 20 mhz crysta l as selected through two bits in the setup2 register, ckup[1,0] as shown below. the selected clock is supplied to the arcnet controller. ckup1 ckup0 clock frequency (data rate) 0 0 20 mhz (up to 2.5mbps) default (bypass) 0 1 40 mhz (up to 5mbps) 1 0 reserved 1 1 80 mhz (only 10mbps) this clock multiplier is powered-down (bypassed) on default. after changing the ckup1 and ckup0 bits, the arcnet core operation is stopped and the internal pll in the clock generator is awakened and it starts to generate the 40 mhz or 80 mhz. the lock out time of the internal pll is 8usec typically. after more than 8 sec (this wait time is defined as 1 msec in th is data sheet), it is necessary to write command data '18h' to the command register to re-start the arcne t core operation. this clock generator is called ?clock multiplier?. changing the ckup1 and ckup0 bits must be one time or less after releasing a hardware reset. the ef bit in the setup2 register must be set when the data rate is over 5 mbps. 4.3 network reconfiguration a significant advantage of the com2 0022i is its ability to adapt to changes on the network. whenever a new node is activated or deactivated, a netw ork reconfiguration is performed. when a new com20022i is turned on (creating a new active node on the network), or if the com20022i has not received an invitation to transmit for 210ms, or if a software reset occurs, the com20022i causes a network reconfiguration by sending a reco nfigure burst consisting of eight marks and one space repeated 765 times. the purpose of this burst is to terminate all activity on the network. since this burst is longer than any other type of transmission, the burst will in terfere with the next invitation to transmit, destroy the token and keep any ot her node from assuming control of the line. when any com20022i senses an id le line for greater than 20.5 s, which occurs only when the token is lost, each com20022i starts an internal timeout equal to 36.5 s times the quantity 255 minus its own id. the com20022i starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing the destination node id . if the timeout expires with no line activity, the com20022i starts sending invitat ion to transmit with the destination id (did) equal to the currently stored nid. within a given network, only one com20022i will timeout (the one with the highest id number). after sending the invitation to transm it, the com20022i waits for activity on the line. if there is no activity for 18.7 s, the com20022i increments the nid value and transmits another invitation to transmit using the nid equal to the did. if activity appears before the 18.7 s timeout expires, the com20022i releas es control of the line. du ring network reconfiguration, invitations to transmit are sent to all nids (1-255). each com20022i on the network will finally have sa ved a nid value equal to the id of the com20022i that it released control to. at this point, control is passed directly from one node to the next with no wasted invitations to transmit being sent to id's not on the network, until the next network reconfiguration occurs. when a node is powered of f, the previous node attempts to pass the token to it by issuing an invitation to transmit. si nce this node does not respond, the previous node times out and transmits another invitation to transmit to an incremented id and eventually a response will be received.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 14 smsc com20022i datasheet the network reconfiguration time depends on the number of nodes in the network, the propagation delay between nodes, and the highest id nu mber on the network, but is typically within the range of 6 to 15.3 ms. 4.4 broadcast messages broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously. id zero is reserved for this featur e and no node on the network can be assigned id zero. to broadcast a message, the transmitting node's processor simply loads the ram buffer with the data packet and sets the did equal to zero. figure 5.7 ill ustrates the position of each byte in the packet with the did residing at address 0x01 or 1 hex of the curr ent page selected in the "enable transmit from page fnn" command. each individual node has the ability to ignore broadcast messages by setting the most significant bit of the "enable receive to page fnn" command (see table 6.5) to a logic "0". 4.5 extended timeout function there are three timeouts associated with the com200 22i operation. the values of these timeouts are controlled by bits 3 and 4 of t he configuration register and bi t 5 of the setup 1 register. 4.5.1 response time the response time determines the maximum propagation delay allowed between any two nodes, and should be chosen to be larger than the round trip pr opagation delay between the two furthest nodes on the network plus the maximum turn around time (the time it takes a particular com20022i to start sending a message in response to a received message) which is approximately 3.2 s. the round trip propagation delay is a function of the transmission media and network topology. for a typical system using rg62 coax in a baseband system, a one way ca ble propagation delay of 7.75 s translates to a distance of about 1 mile. the flow chart in figure 3. 1figure 2.1 uses a value of 18.7 s (7.75 + 7.75 + 3.2) to determine if any node will respond. 4.5.2 idle time the idle time is associated with a network re configuration. figure 3.1fig ure 2.1 illustrates that during a network reconfiguration one node will continually transmit invitations to transmit until it encounters an acti ve node. all other nodes on the ne twork must distinguish between this operation and an entirely idle line. during ne twork reconfiguration, activity will appear on the line every 20.5 s. this 20.5 s is equal to the response time of 18.7 s plus the time it takes the com20022i to start retransmitting another message (usually another invitation to transmit). 4.5.3 reconfiguration time if any node does not receive the token within the reco nfiguration time, the node will initiate a network reconfiguration. the et2 and et1 bits of the conf iguration register allow the network to operate over longer distances than the 1 m ile stated earlier. the logic levels on these bits control the maximum distances over which the com20022i can operate by controlling the thre e timeout values described above. for proper network operation, all com20022i's c onnected to the same network must have the same response time, idle time, and reconfiguration time.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 15 rev. 08-18-03 datasheet 4.6 line protocol the arcnet line protocol is consider ed isochronous because each byte is preceded by a start interval and ended with a stop interval. unlike asynchronous pr otocols, there is a c onstant amount of time separating each data byte. on a 10 mbps network, each byte takes exactly 11 clock intervals of 100ns each. as a result, one byte is transmitted every 1.1 s and the time to transmit a message can be precisely determined. the line idles in a spacing (logi c "0") condition. a logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 50ns duration. a transmission starts with an alert burst consisting of 6 unit intervals of mark (l ogic "1"). eight bit data characters are then sent, with each character preceded by 2 unit intervals of ma rk and one unit interval of space. five types of transmission can be performed as described below: 4.6.1 invitations to transmit an invitation to transmit is used to pass the token from one node to another and is sent by the following sequence: an alert burst an eot (end of transmission: ascii code 04h) two (repeated) did (destination id) characters alert burst eot did did 4.6.2 free buffer enquiries a free buffer enquiry is used to ask another node if it is able to accept a packet of data. it is sent by the following sequence: an alert burst an enq (enquiry: ascii code 85h) two (repeated) did (destination id) characters alert burst enq did did 4.6.3 data packets a data packet consists of the actual data being sent to another node. it is sent by the following sequence: an alert burst an soh (start of header--ascii code 01h) an sid (source id) character two (repeated) did (destination id) characters a single count character which is the 2's complement of the number of data bytes to follow if a short packet is sent, or 00h followed by a count character if a long packet is sent. n data bytes where count = 256-n (or 512-n for a long packet) two crc (cyclic redundancy check) characters. the crc polynomial used is: x 16 + x 15 + x 2 + 1. a lert burst soh sid did did count data data crc crc
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 16 smsc com20022i datasheet 4.6.4 acknowledgements an acknowledgement is used to acknowledge reception of a packet or as an affirma tive response to free buffer enquiries and is sent by the following sequence: an alert burst an ack (acknowledgement--ascii code 86h) character alert burst ack 4.6.5 negative acknowledgements a negative acknowledgement is used as a negative response to free buffer enquiries and is sent by the following sequence: an alert burst a nak (negative acknowledgement--ascii code 15h) character alert burst nak
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 17 rev. 08-18-03 datasheet chapter 5 system description 5.1 microcontroller interface the top halves of figure 5.1 and figure 5.2 illustrate typical com20022i interfaces to the microcontrollers. the interfaces consist of a 8-bit data bus, an a ddress bus and a control bus. in order to support a wide range of microcontrollers without requiring glue lo gic and without increasing the number of pins, the com20022i automatically detects and adapts to the ty pe of microcontroller being used. upon hardware reset, the com20022i first determines whether the re ad and write control signals are separate read and write signals (like the 80xx) or direction and data strobe (like the 68xx). to determine the type of control signals, the device requires the software to execute at least one write access to external memory before attempting to access the com20022i. the device def aults to 80xx-like signals. once the type of control signals are determined, the com20022i remain s in this interface mode until the next hardware reset occurs. the second determination the com20022i makes is whether the bus is multiplexed or non- multiplexed. to determine the type of bus, the devi ce requires the software to write to an odd memory location followed by a read from an odd location befo re attempting to access the com20022i. the signal on the a0 pin during the odd location access tells th e com20022i the type of bus. since multiplexed operation requires a0 to be active low , activity on the a0 line tells th e com20022i that the bus is non- multiplexed. the device defaults to multiplexed operation. both determinations may be made simultaneously by performing a write followed by a read operation to an odd location within the com20022i address space 20022 registers. once the type of bus is determined, the com20022i remains in this interface mode until hardware reset occurs. whenever ncs and nrd are activated, the preset deter minations are assumed as final and will not be changed until hardware reset. refer to description of pin functions section for details on the related signals. all accesses to the internal ram and the in ternal registers are controlled by the com20022i. the internal ram is accessed via a pointer-based scheme (refer to the sequential access memory section), and the internal registers are accessed via direct addressing. many peripherals are not fast enough to take advantage of high-speed microcontrollers. since microcontrollers do not typically have ready inputs, standard peripherals cannot extend cycles to extend t he access time. the access time of the com20022i, on the other hand, is so fast that it does not need to limit the s peed of the microcontroller. the com20022i is designed to be flexible so that it is independent of the microcontroller speed. the com20022i provides for no wait st ate arbitration via direct addressi ng to its internal registers and a pointer based addressing scheme to access its internal ram. the pointer may be used in auto-increment mode for typical sequential buffer emptying or loading, or it can be taken out of auto-increment mode to perform random accesses to the ram. the data within the ram is accessed th rough the data register. data being read is prefetched from memory and placed into the data register for the microcontroller to read. it is important to notice that only by writing a ne w address pointer (writing to an address pointer low), one obtains the contents of com20022i internal ram. performing only read from the data register does not load new data from the internal ram . during a write operation, the data is stored in the data register and then written into memory. whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepar e for the first read operation.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 18 smsc com20022i datasheet a d0-ad7 nint1 reset nrd nwr a 15 a d0-ad2, d3-d7 ncs nreset nrd/nds nwr/dir nintr a 2/bale a le xtal1 xtal2 gnd rxin npulse1 npulse2 ntxen 8051 com2002i differential driver configuration media interface may be replaced with figure a, b or c. * rxin npulse1 npulse2 txen gnd +5v 100 ohm backplane configuration figure a rxin npulse1 figure b receiver hfd3212-002 2 +5v 7 6 transmitter hfe4211-014 +5v 3 2 fiber interface (st connectors) 2 6 7 note: com20022i must be in backplane 75176b or equiv. a 0/nmux 27 pf 27 pf xtal2 xtal1 20 mhz xtal figure 5.1 - multiplexed, 8051-like bus interface with rs-485 interface
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 19 rev. 08-18-03 datasheet d0-d7 nirq1 nres nios r/nw a 7 d0-d7 a 0/nmu x a 0 xtal1 xtal2 a 1 a 1 ncs nreset nrd/nds nwr/ndir nintr a 2/bale a 2 rxin npulse1 npulse2 txen gnd differential driver configuration 6801 com20022i media interface may be replaced with figure a, b or c. * 75176b or equiv. xtal1 xtal2 27 pf 27 pf 20mhz xtal rxin npulse1 npulse2 ntxen gnd traditional hybrid configuration rxin npulse1 npulse2 17, 19, 4, 13, 14 5.6k 1/2w 5.6k 1/2w 0.01 uf 1kv 12 11 -5v 0.47 uf 10 uf + 3 0.47 uf + +5v uf 10 6 figure c hyc9088 hyc9068 or n/c *valid for 2.5 mbps only. figure 5.2 - non-multiplexed, 6801-like bus interface with rs-485 interface
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 20 smsc com20022i datasheet 5.1.1 selection of 8/16-bit access the interface to the internal ram is software selectabl e as either 8 or 16-bit. this feature is new to the com20022i. the d15-d8 pins are t he upper-byte data bu s pins. the niocs16 pi n is the 16-bit i/o access enable output pin. this pin is active low for a 16-bit ram access by the cpu (not a dma access). the 16-bit access mode is enabled and disabled through the w16 bit located in the bus control register at bit 7. the swap bit is used to swap the upper an d lower data bytes in 16-bit mode, as shown in the table below. the swap bit is located at bit 0 of addre ss low pointer. this locati on is same as the a0 bit; when 16 bit access is enabled (w16 =1), the a0 bit becomes the swap bit. detected host i/f mode swap bit (note) d15-d8 pins d7-d0 pins intel 80xx mode (rd,wr mode) 0 1 odd even even odd motorola 68xx mode (dir, ds mode) 0 1 even odd odd even note: the swap bit is undefined after a hardware reset as shown on the table above, ev en address data is to/from d7-d0 pi ns and odd address data is to/from d15-d8 pins when detected host interface mode is intel 80xx mode and the swap bit is not set. the odd address data is to/from the d7-d0 pins and the even address data is to/from d15-d8 pins when detected host interface mode is motorola 68xx mode and the swap bit is not set. when disabling 16-bit access, the d15-d8 pins are always hi-z. the d15-d8 pins are hi-z when enabling 16-bit access except for internal ram access. w16 bit and swap bit influence both the cpu cycle and dma cycle. 5.1.2 dma transfers to and from internal ram the com20022i supports dma transfers to and from the internal ram. this feature is new to the com20022i. the software selectable 8/16 bit interf ace to the ram pertains to dma transfers. when the w16 bit=0, the microcontroller interface and dma tran sfers are both 8-bit data transfers to/from internal ram. when w16=1 they are both 16-bit data transfe rs. an 8-bit microcontroller interface and 16-bit dma data transfer cannot be selected; they must be the sa me width data transfers to/from internal ram. the data swapping operation on 16-bit data transfers also pertains to both. the dma interface consists of several added pins . the dreq pin is the dma request output pin. the active polarity of this pin is program mable; the default is active-high. the ndack pin is the active-low dma acknowledge input pin. the tc pin is the external te rminal count input pin. this pin determines when the ndack pin is active. it?s active polarity is programmable; the default is active-high. the nrefex pin is the active-low refresh execution pulse input pin. the dma interface is controlled by the following bits . the dmaend bit selects whether or not to mask the interrupt upon finishing the dma. this bit is located at bit 4 of the mask register. the dmaen bit is used to disable/enable the assertion of the dma request (dreq pin) after writing the address pointer low register. this bit is located in the address pointer high register, bit 3. the following bits are located in the bus control register: drpol, tcpol and dmamd[1,0]. the drqpol bit sets the active polarity of the dreq pin; the tcpol bit sets the active polarity of the tc pin; the dmamd[1,0] bits select the data transfer mode of the dma. the itcen/rtrg bit has one of two functions, depe nding on the dma transfer mode selected. itcen is the internal terminal counter enable. it is used to se lect whether the dma is terminated by external tc
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 21 rev. 08-18-03 datasheet only or by either internal or external tc. itcen is for non-burst or burst mode. rtrg selects the re- trigger mode as either external or internal. it is for the two programmable-burst modes. the tc8/rsyn/gttm bit has one of three functions, depending on the dma transfer mode selected. tc8 is bit 8 of the terminal count. it is the msb of the 9 bi t terminal count setting register (the other 8 bits are in the dma count register). tc8 is for non-burst or burst mode. rsyn is the refresh synchronous bit. this bit is used to select whether the dma is start ed immediately or after refresh execution. gttm is the gate time bit. this bit selects whether the gate time is 350ns (min) or 750ns (min). rsyn and gttm are for the two programmable-burst modes. rsyn is fo r external re-trigger mode; gttm is for internal re-trigger mode. located in the dma count register, the tc7-tc0 /t im7-tim0 /cyc7-cyc0 bits have one of three functions depending on the dma transfer mode. tc7-tc 0 are for non-burst or bur st mode. these are the lower 8 bits of the terminal count setting register (the msb is in the bus control register). the tim7- tim0 bits are for setting the time of the continuous dma transfer in programmable-burst by timer mode. the cyc7-cyc0 bits are for setting the time of the continuous dma transfer in programmable-burst by cycle mode. 5.1.3 dma operation the dma interface operates in one of four trans fer modes: non-burst, burst, programmable-burst (by timer) and programmable-burst (by cycle counter). the dat a transfer mode of the dma is selected through the dmamd[1,0] bits in the bus control regist er, bits [3,2]. these modes are described below. non-burst mode is a single transfer mode wherein, the dreq pin is asserted after writing the address pointer low register when dmaen=1. actually, dreq pin is asserted 4t arb time after writing the address pointer low register when dmaen = 1 (refer to figure 5.3). this mode operates as follows: 1. the ndack pin is asserted by the dma controller detecting the dreq pin asserted. 2. the dreq pin is deasserted by the com2 0022i detecting the ndack pin asserted. 3. the ndack pin is deasserted by the dma cont roller detecting the dreq pin deasserted after executing the present read or write cycle. 4. the dreq pin is asserted by the com2 0022i detecting the dack pin deasserted. repeat above 4 steps until the tc pin goes acti ve. this mode is called "cycle steal mode". burst mode is a demand transfer mode. in this mode, the dreq pin is asserted after writing the address pointer low register when dmaen=1. actually, dreq pin is asserted 4t arb time after writing the address pointer low register when dmaen = 1 (refer to figure 5.3). the dack pin is asserted by the dma controller detecting the dreq pin asserted. t he dreq pin stays asserted until the tc pin goes high. programmable-burst mode is a demand transfer mode with temporary dreq deassertion for a refresh cycle. the dreq pin is asserted after writing the a ddress pointer low register when dmaen=1 (refer to figure 5.3). the dack pin is asserted by the dma controller detecting the dreq pin asserted. if the continuous dma operation time is longer than th e set refresh period, then dreq is deasserted. the dreq is held deasserted after negating ndack for the ga te time. after the gate time, the dreq pin is asserted again. the dreq pin stays asserted until the tc pin goes high. in programmable-burst mode, the gating can be by timer or by cycle counter.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 22 smsc com20022i datasheet dreq nwr dmaen bit writing address pointer low minimum 4t arb t arb is the arbitration clock period. it depends on the t opr and slow-arb bit. t opr is the period of operation clock frequency (output of the clock multiplier). it depends on the ckup1 and ckup0 bits. t arb = t opr @ slow-arb = 0 t arb = 2 t opr @ slow-arb = 1 figure 5.3 - dreq pin first assertion timing for all dma modes as an example of gating by cycle, in an isa bus system, the refresh period is 15 s. continuous transfer by dma must be less than 15 s to prevent blocking by the refresh cycle. a dma cycle of consecutive dma cycles is approximately 1us. the dma overhead time is approximately 2.5 s. the refresh execution time is 500ns. this computes to 15 s - 2.5 s - 500ns = 12 s or 12 cycles. therefore the dreq pin must be negated every 12 cycles. figure 5.4 illustrates the rough timi ng of the programmable- burst mode dma transfer.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 23 rev. 08-18-03 datasheet figure 5.4 - programmable burst mode dma transfer (rough timing) the timing of the non-burst mode dma data transfer is found in the timing diagrams section of this data sheet. the basic sequence of operation is as follows: ndack becomes active (low) upon dreq becoming active (high) and catching the host bus (aen=1). dreq becomes inactive after ndack and read/write signal become active. dreq becomes active after ndack or read/write signal becomes inactive. dreq becomes inactive after tc and the read/write signal assert (when ndack=0). in this case, dreq doesn't become active again after ndack becomes inactive. ndack becomes inactive after dreq=0 and the present cycle finishes. gate time dreq (active-high) ndack (active-low) transfer term (counting read/write pulse or counting internal timer) restart transfer
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 24 smsc com20022i datasheet the following rough timing diagram of the non-burst m ode dma data transfer is included for illustration purposes. figure 5.5 - non-burst mode dma data transfer rough timing the timing of the burst mode dma data transfer is found in the timing diagr ams section of this data sheet. the basic sequence of operation is as follows: ndack becomes active (low) upon dreq becoming active (high) and catching the host bus (aen= ?1?). dreq becomes inactive after tc asserts (when ndack= ?0?). in this case, dreq doesn't become active again after ndack becomes inactive. ndack becomes inactive after dreq= 0 and the present cycle finishes. the following rough timing diagram of the non-burst m ode dma data transfer is included for illustration purposes. figure 5.6 - burst mode dma data transfer rough timing dreq ndack tc read/write signal dreq ndack tc read/write signal
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 25 rev. 08-18-03 datasheet the following sequences show the data transfer for a dma read and a dma write. the transfer of data between system memory and internal ram functions as a memory to i/o dm a transfer. since it is treated as an i/o device, the com2 0022i has to create the ram address. therefore t he com20022i?s address pointers must be programmed before starting the dma transfers. 5.1.4 dma data transfer sequence (i/o to memory: read a packet) step1: set dma-controller (ex. 8237) step2: set drqpol, tcpol, dmamd1 and dmamd0 bits >>finished dma setup >>a packet received step3: set address, byte count an d etc. of dma controller step4: set pointer high and low (rddata=1,autoinc=1, dmaen=0) step5: read sid, did, cp in the received packet step6: set dmaen=1 (rddata=1, autoinc=1) step7: dmaend=1 in mask reg. step8: set pointer = cp >>dreq is asserted by step8 >>interrupt occurs upon finishing dma 5.1.5 dma data transfer sequence (memory to i/o: write a packet) step1: set dma-controller (ex. 8237) step2: set drqpol, tcpol, dmamd1 and dmamd0 bits >>finished dma setup step3: set address, byte count and etc. of dma controller step4: set pointer high and low (rddata=0,autoinc=1, dmaen = 0) step5: write sid,did,cp in the sending packet step6: set dmaen=1 (rddata=0, autoinc=1) step7: dmaend=1 in mask reg. step8: set pointer = cp >>dreq is asserted by step8 >>interrupt occurs upon finishing dma transfer step9: write enable transmit command to command register 5.1.6 high speed cp u bus timing support high speed cpu bus support was added to the com20022i. the reasoning behind this is as follows: with the host interface in no n-multiplexed bus mode, i/o address and chip select signals must be stable before the read signal is active and remain after the read signal is inactive. but the high speed cpu bus timing doesn't adhere to these timings. for example, a risc type single chip microcontroller (like the hitachi sh-1 series) changes i/o address at the same time as the read signal. therefore, several external logic ics would be required to connect to this microcontroller. in addition, the diagnostic status (diag) register is cl eared automatically by reading itself. the internal diag register read signal is gener ated by decoding the address (a2-a0), chip select (ncs) and read (nrd) signals. the decoder will generate a noise spik e at the above tight timing. the diag register is cleared by the spike signal without reading itself. this is unexpected operation. reading the internal ram and next id register have the same me chanism as reading the diag register. therefore, the address decode an d host interface mode blocks were modified to fit the above cpu interface to support high speed cpu bus timing. in intel cpu mode (nrd, nw r mode), 3 bit i/o address (a2-a0) and chip select (ncs) are sampled internally by flip-flops on the falling edge of the internal delayed nrd signal. the internal real read signal is the more delayed nrd signal. but the rising edge of nrd doesn't delay. by this modification, the internal real address and chip select are stable while the internal real read signal is active. refer to figure 5.7 on the following page.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 26 smsc com20022i datasheet figure 5.7 - high speed cpu bus timing - intel cpu mode the i/o address and chip select signals, which are s upplied to the data output logic, are not sampled. also, the nrd signal is not delayed, because the ab ove sampling and delaying paths decrease the data access time of the read cycle. the above sampling and delaying signals are supplied to the read pulse generation logic which generates the clearing pulse for the diagnostic regi ster and generates the st arting pulse of the ram arbitration. typical delay time between nrd and nrd1 is around 15ns and between nrd1 and nrd2 is around 10ns. longer pulse widths are needed due to these delays on nrd signal. however, the cpu can insert some wait cycles to extend the width without any impact on performance. the bustmg pin is used to support this function. it is used to enable/disable the high speed cpu read and write function. it is defined as : bustmg = 0, the high speed cpu read and write operations are enabled; bustmg = 1, the high speed cpu read and write operations are disabled if the rbustmg bit is 0. if bustmg = 1 and rbustm g = 1, high speed cpu read operations are enabled (see definition of rbustmg bit below). the rbustmg bit was added to disable/enable the high speed cpu read function. it is defined as: rbustmg=0, disabled (default); rbustmg=1, enabled. in the motorola cpu mode (dir, nds mode), the same modifications apply. bustmg pin rbustmg bit bus timing mode 0 x high speed cpu read and write 1 0 normal speed cpu read and write 1 1 high speed cpu read and normal speed cpu write 5.2 transmission media interface the bottom halves of figure 5.1 and figure 5.2 ill ustrate the com20022i interface to the transmission media used to connect the node to the network. table 5.1 lists different types of cable which are suitable for arcnet applications. the user may interface to the cable of choice in one of three ways: a2-a0, ncs nrd delayed nrd (nrd1) sampled a2-a0, ncs more delayed nrd (nrd2) valid valid
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 27 rev. 08-18-03 datasheet 5.2.1 traditional hybrid interface the traditional hybrid interface is that which is used with previous arcnet devices. the hybrid interface is recommended if the node is to be placed in a network with other hybrid-interfaced nodes. the traditional hybrid interface is for use with nodes oper ating at 2.5 mbps only. the transformer coupling of the hybrid offers isolation for the safety of the sy stem and offers high common mode rejection. the traditional hybrid interface uses circuits like smsc 's hyc9068 or hyc9088 to transfer the pulse-encoded data between the cable and the com20022i. the co m20022i transmits a logic "1" by generating two 100ns non-overlapping negative pulses, npulse1 and npulse2. lack of pulses indicates a logic "0". the npulse1 and npulse2 signals are sent to the hybr id, which creates a 200ns dipulse signal on the media. a logic "0" is transmitted by the absence of the dipulse. during reception, the 200ns dipulse appearing on the media is coupled through the rf transformer of the lan driver, which produces a positive pulse at the rxin pin of the com20022i. the pulse on the rxin pin represents a logic "1". lack of pulse represents a logic "0". typically, rxin pu lses occur at multiples of 400ns. the com20022i can tolerate distortion of plus or minus 100ns and still correctly capture and convert the rxin pulses to nrz format. figure 5.4 illustrates the events which occur in transmission or reception of data consisting of 1, 1, 0. 5.2.2 backplane configuration the backplane open drain configuration is recommended for cost-sensitive, short- distance applications like backplanes and instrumentation. this mode is advantageous because it saves components, cost, and power. since the backplane configuration encodes data differently than the tr aditional hybrid configuration, nodes utilizing the backplane conf iguration cannot communicate directly with nodes utilizing the traditional hybrid configuration. the backplane conf iguration does not isolate the node from the media nor protects it from common mode noise, but co mmon mode noise is less of a problem in short distances. the com20022i supplies a programma ble output driver for backplane mode operation. a push/pull or open drain driver can be selected by programming the p1 mode bit of the setup 1 register (see register descriptions for details). the com200 22i defaults to an open drain output. the backplane configuration provides for direct co nnection between the com20022i and the media. only one pull-up resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each individual no de). the npulse1 signal, in this mode, is an open drain or push/pull driver and is used to directly drive the media. it issues a 200ns negative pulse to transmit a logic "1". note that when used in the open-drain mode, the co m20022i does not have a fail/safe input on the rxin pin. the npulse1 signal actually contains a weak pull-up resist or. this pull-up should not take the place of the resistor required on the media for open drain mode.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 28 smsc com20022i datasheet figure 5.8 - com20022i network using rs-485 differential transceivers figure 5.9 - dipulse waveform for data of 1-1-0 in typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor. the rxin signal is directly connected to the cable via an internal schmitt trigger. a negative pulse on this input indicates a logic "1". lack of pulse indicates a logic "0". for typical single-ended backplane applications, rxin is connected to npulse1 to make the serial backplane data line. a ground line (from the coax or twisted pair) should run in parallel with th e signal. for applications requiring different treatment of the receive signal (like filtering or squelching ), npulse1 and rxin remain as independent pins. external differential drivers/receivers for increased range and common mode noise rejection, for example, would require the signals to be independent of one an other. when the device is in backplane mode, the clock provided by the npulse2 signal may be used for encoding the data into a different encoding scheme or other synchronous operations needed on the serial data stream. 20mhz clock (for ref. only) npulse1 npulse2 dipulse rxin 10 100ns 100ns 200ns 400ns 1 com20022i com20022i com20022i +vcc rbias +vcc +vcc rbias rbias rt rt 75176b or equiv.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 29 rev. 08-18-03 datasheet 5.2.3 differential dr iver configuration the differential driver configuration is a special case of the backplane mode. it is a dc coupled configuration recommended for applications like car-area networks or other cost-sensitive applications which do not require direct compatibility with existing arcnet nodes and do not require isolation. the differential driver configuration ca nnot communicate directly with nodes utilizing the traditional hybrid configuration. like the backplane configuration, the differential driver configuration does not isolate the node from the media. the differential driver interface includes a rs485 driver/receiver to transfer the data between the cable and the com20022i. the npulse1 signal transmits the data, provided the transmit enable signal is active. the npulse1 signal issues a 200ns (at 2.5mbps) negative pulse to transmit a logic "1". lack of pulse indicates a logic "0". the rxin signal receives the data, the transmitter portion of the com20022i is disabled during reset and the npulse1, npulse2 and ntxen pins are inactive. 5.2.4 programmable txen polarity to accommodate transceivers with active high enable pins, the com20022i contains a programmable txen output. to program the txen pin for an active high pulse, the npulse2 pin should be connected to ground. to retain the normal active low polarity, npulse2 should be left open. the polarity determination is made at power on reset and is valid only for backplane mode operation. the npulse2 pin should remain grounded at all times if an active high polarity is desired. figure 5.10 - internal block diagram micro- sequencer and working registers status/ command register reset logic reconfiguration timer node id logic oscillator tx/rx logic additional registers address decoding circuitry 2k x 8 ad0-ad2, bus arbitration circuitry npulse1 npulse2 ntxen nintr nreset ram a 0 / n m u x a 1 a 2 / b a l e nrd/nds nwr/dir ncs d3-d15 rxin niocs16 xtal1 xtal2 dma dreq ndack tc nrefex
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 30 smsc com20022i datasheet table 5.1 - typical media cable type nominal impedance attenuation per 1000 ft. at 5 mhz rg-62 belden #86262 93 ? 5.5db rg-59/u belden #89108 75 ? 7.0db rg-11/u belden #89108 75 ? 5.5db ibm type 1* belden #89688 150 ? 7.0db ibm type 3* telephone twisted pair belden #1155a 100 ? 17.9db comcode 26 awg twisted pair part #105-064-703 105 ? 16.0db note*: non-plenum-rated cables of this type are also available.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 31 rev. 08-18-03 datasheet chapter 6 functional description 6.1 microsequencer the com20022i contains an internal microsequencer which performs all of the control operations necessary to carry out the arcnet protocol. it consis ts of a clock generator, a 544 x 8 rom, a program counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic. the com20022i derives a 20 mhz and a 10 mhz clock from the output clock of the clock multiplier. these clocks provide the rate at wh ich the instructions ar e executed within the com20022i. the 20 mhz clock is the rate at which the program counter operates, while the 10 mhz clock is the rate at which the instructions are executed. the microprogram is stored in the rom and the instructions are fetched and then placed into the instruction registers. one register holds the opcode, while the other holds the immediate data. once the instruction is fetched, it is decoded by the internal instruction decoder, at which point the com20022i proceeds to execute the instruction. when a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is complete. when a jump instruction is encountered, the program counter is loaded with the jump address from the rom. the com20022i contains an internal reconfiguration timer which interrupts the microsequencer if it has timed out. at this point the program counter is cleared and the myrecon bit of the diagnostic status register is set.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 32 smsc com20022i datasheet table 6.1 - read register summary register msb read lsb addr status ri/tri x/ri x/ta po r test recon tma ta/ tta 00 diag. status my- recon dupid rcv- act token exc- nak tentid new nextid x 01 address ptr high rd- data auto- inc x x dma- en a10 a9 a8 02 address ptr low a7 a6 a5 a4 a3 a2 a1 a0/ swap 03 data* d7 d6 d5 d4 d3 d2 d1 d0 04 sub adr (r/w)* 0 0 0 (r/w)* sub- ad2 sub- ad1 sub- ad0 05 config- uration reset cchen txen et1 et2 back- plane sub- ad1 sub- ad0 06 tentid tid7 tid6 tid5 tid4 tid3 tid2 tid1 tid0 07-0 node id nid7 nid6 nid5 nid4 nid3 nid2 nid1 nid0 07-1 setup1 p1 mode four naks x rcv- all ckp3 ckp2 ckp1 slow- arb 07-2 next id nxt id7 nxt id6 nxt id5 nxt id4 nxt id3 nxt id2 nxt id1 nxt id0 07-3 setup2 rbus- tmg x ckup1 ckup0 ef no- sync rcn- tm1 rcm- tm2 07-4 bus control w16 x itcen/ rtrg tc8/ rsyn/ gttm dma- md1 dma- md0 tcpol drq- pol 07-5 dma count tc7/ tim7/ cyc7 tc6/ tim6/ cyc6 tc5/ tim5/ cyc5 tc4/ tim4/ cyc4 tc3/ tim3/ cyc3 tc2/ tim2/ cyc2 tc1/ tim1/ cyc1 tc0/ tim0/ cyc0 07-6 note*: this bit can be written and read. *data register at 16 bit access register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr data d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 04
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 33 rev. 08-18-03 datasheet table 6.2 - write register summary addr msb write lsb register 00 ri/tr1 0 0 dma end excnak recon new nextid ta/ tta interrupt mask 01 c7 c6 c5 c4 c3 c2 c1 c0 command 02 rd- data auto- inc 0 0 dmaen a10 a9 a8 address ptr high 03 a7 a6 a5 a4 a3 a2 a1 a0/ swap address ptr low 04 d7 d6 d5 d4 d3 d2 d1 d0 data* 05 (r/w)* 0 0 0 (r/w)* sub- ad2 sub- ad1 sub- ad0 subadr 06 reset cchen txen et1 et2 back- plane sub- ad1 sub- ad0 config- uration 07-0 tid7 tid6 tid5 tid4 tid3 tid2 tid1 tid0 tentid 07-1 nid7 nid6 nid5 nid4 nid3 nid2 nid1 nid0 nodeid 07-2 p1- mode four naks 0 rcv- all ckp3 ckp2 ckp1 slow- arb setup1 07-3 0 0 0 0 0 0 0 0 test 07-4 rbus- tmg 0 ckup1 ckup0 ef no- sync rcn- tm1 rcn- tm0 setup2 07-5 w16 0 itcen/ rtrg tc8/ rsyn/ gttm dma- md1 dma- md0 tc- pol drq- pol bus control 07-6 tc7/ tim7/ cyc7 tc6/ tim6/ cyc6 tc5/ tim5/ cyc5 tc4/ tim4/ cyc4 tc3/ tim3/ cyc3 tc2/ tim2/ cyc2 tc1/ tim1/ cyc1 tc0/ tim0/ cyc0 dma count note*: this bit can be written and read. *data register at 16 bit access register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr data d 15 d 14 d 13 d 12 d 11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 04 6.2 internal registers the com20022i contains 16 internal registers. t able 6.1 and table 6.2 illustrate the com20022i register map. all undefined bits are read as undefined and must be written as logic "0". 6.2.1 interrupt mask register (imr) the com20022i is capable of generating an interrupt signal when certain status bits become true. a write to the imr specifies which status bits will be enabled to generate an interrupt. the bit positions in the imr are in the same position as their corresponding status bits in the status register and diagnostic status register. a logic "1" in a particular position enables the corresponding interrupt. the status bits capable of generating an interrupt include the receiver inhibited bit, dmaend bit (new to the com20022i), new next
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 34 smsc com20022i datasheet id bit, excessive nak bit, reconfiguration timer bit, and transmitter available bit. dmaend bit is inverted dmaen bit on address ptr high register. no ot her status or diagnostic status bits can generate an interrupt. the six maskable status bits are anded with their respective mask bits, and the results are ored to produce the interrupt signal. an ri or ta interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this time. a recon interrupt is cleared when the "clear flags" command is issued. an excnak interrupt is cleared when the "por clear flags" command is issued. a new next id interrupt is cleared by reading the next id register. if the dmaend bit is not masked, the interrupt occurs by finishing the dma operation. the interrupt mask register defaults to the value 0000 0000 upon hardware reset. 6.2.2 data register this read/write 8-bit register is used as the channel through which the data to and from the ram passes. the data is placed in or retrieved from the address location presently specified by the address pointer. the contents of the data register are undefined upon hardware reset. in case of read operation, the data register is loaded with the contents of com20022i internal memory upon writing address pointer low only once. the swap bit is used to swap the upper and lower data byte. the swap bit is located at bit 0 of address ptr_low register. when 16 bit access is enabled, (w16=1), a0 becomes the swap bit. 6.2.3 tentative id register the tentative id register is a read/write 8-bit r egister accessed when the sub address bits are set up accordingly (please refer to the configuration register and sub adr register). the tentative id register can be used while the node is on-line to build a network map of those nodes existing on the network. it minimizes the need for operator interaction with the network. the node determines the existence of other nodes by placing a node id value in the tentative id register and waiting to see if the tentative id bit of the diagnostic status register gets set. the network map developed by this method is only valid for a short period of time, since nodes may join or depart from the network at any time. when using the tentative id feature, a node cannot detect the existence of the next logical node to which it passes the token. the next id register will hold the id value of that node. the tentative id register defaults to the value 0000 0000 upon hardware reset only. 6.2.4 node id register the node id register is a read/write 8-bit register accessed when the sub address bits are set up accordingly (please refer to the configuration register and sub adr register). the node id register contains the unique value which identifies this particular node. each node on the network must have a unique node id value at all times. the duplicate id bit of the diagnostic status register helps the user find a unique node id. refer to the initialization sequence section for further detail on the use of the dupid bit. the core of the com20022i does not wake up until a node id other than zero is written into the node id register. during this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node. once a non-zero nodeid is placed into the node id register, the core wakes up but will not join the network until the txen bit of the configuration register is set. while the transmitter is disabled, the receiver por tion of the device is still functional and will provide the user with useful information about the network. the node id regi ster defaults to the value 0000 0000 upon hardware reset only.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 35 rev. 08-18-03 datasheet 6.2.5 next id register the next id register is an 8-bit, read-only regist er, accessed when the sub-address bits are set up accordingly (please refer to the configuration register and sub adr register). the next id register holds the value of the node id to which the com20022i will pass the token. when used in conjunction with the tentative id register, the next id register can provide a complete network map. the next id register is updated each time a node enters/leaves the network or when a network reconfiguration occurs. each time the microsequencer updates the next id regi ster, a new next id interrupt is generated. this bit is cleared by reading the next id register. default value is 0000 0000 upon hardware or software reset. 6.2.6 status register the com20022i status register is an 8-bit read-only regi ster. all of the bits, except for bits 5 and 6, are software compatible with previous smsc arcnet devices. in previous smsc arcnet devices the extended timeout status was provided in bits 5 and 6 of the status register. in the com20022i, the com20020, the com90c66, and the com90c165, com20020-5, com20051 and com20051+ these bits exist in and are controlled by the configuration register. the status register contents are defined as in table 6.3, but are defined differently during the command chaining operation. please refer to the command chaining section for the definition of the status register during command chaining operation. the status register defaults to the value 1xx1 0001 upon either hardware or software reset. 6.2.7 diagnostic status register the diagnostic status register contains seven read-only bits which help the user troubleshoot the network or node operation. various combinations of these bits and the txen bit of the configuration register represent different situations. all of these bits, except the excessive nack bit and the new next id bit, are reset to logic "0" upon reading the diagnostic status register or upon software or hardware reset. the excnak bit is reset by the "por clear flags" command or upon software or hardware reset. the diagnostic status register defaults to the value 0000 000x upon either hardware or software reset. 6.2.8 command register execution of commands are initiated by performing microcontroller writes to this register. any combinations of written data other than those listed in table 6.5 are not permitted and may result in incorrect chip and/or network operation. 6.2.9 address pointer registers these read/write registers are each 8-bits wide and are used for addressing the internal ram. new pointer addresses should be written by first writing to the high register and then writing to the low register because writing to the low register loads the address. the contents of the address pointer high and low registers are undefined upon hardware reset. writing to address pointer low loads the address. the dmaen bit (new to the com20022i) is located at bit 3 of the address ptr high register. the dmaen bit is used to disable/enable the assertion of the dma request (dreq pin) after writing the address pointer low register. the swap bit (new to the com20022i) is located at bit 0 of address pointer low register. the swap bit is used to swap the upper and lower data byte. when 16 bit access is enabled, (w16=1), a0 becomes the swap bit.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 36 smsc com20022i datasheet 6.2.10 configuration register the configuration register is a read/write register which is used to configure the different modes of the com20022i. the configuration register defaults to the value 0001 1000 upon hardware reset only. subad0 and subad1 point to the selection in register 7. 6.2.11 sub-address register the sub-address register is new to the com20022i, previously a reserved register. bits 2, 1 and 0 are used to select one of the registers assigned to address 7h. subad1 and subad0. they are exactly same as those in the configuration register. if the subad1 and subad0 bits in the configuration register are changed, the subad1and subad0 in the sub-address register are also changed. subad2 is a new sub- address bit. it is used to access the 3 new set up r egisters, setup2, bus control and dma count. these registers are selected by setting subad2=1. the subad2 bit is cleared automatically by writing the configuration register. write bits[7:3] to ?0? for proper operation. 6.2.12 setup 1 register the setup 1 register is a read/write 8-bit register accessed when the sub address bits are set up accordingly (see the bit definitions of the configuration register). the setup 1 register allows the user to change the network speed (data rate) or the arbitration speed independently, invoke the receive all feature and change the npulse1 driver type. the data rate may be slowed to 156.25kbps and/or the arbitration speed may be slowed by a factor of two. the setup 1 register defaults to the value 0000 0000 upon hardware reset only. 6.2.13 setup 2 register the setup 2 register is new to the com20022i. it is an 8-bit read/write register accessed when the sub address bits subad[2:0] are set up accordingly (see the bit definitions of the sub address register). this register contains bits for various functions. the ckup1,0 bits select the clock to be generated from the 20 mhz crystal. the rbustmg bit is used to disable/enable fast read function for high speed cpu bus support. the ef bit is used to enable the new timing for certain functions in the com20022i (if ef = 0, the timing is the same as in the com20020 rev. b). see appendix ?a?. the nosync bit is used to enable the nosync function during initialization. if this bit is reset, the line has to be idle for the ram initialization sequence to be written. if set, the line does not have to be idle for the initialization sequence to be written. see appendix ?a?. the rcntm[1,0] bits are used to set the time-out perio d of the recon timer. programming this timer for shorter time periods has the benefit of shortened network reconfiguration periods. the time periods shown in the table on the following page are limited by a maximum number of nodes in the network. these time- out period values are for 10mbps. for other data rates, scale the time-out period time values accordingly; the maximum node count remains the same. rcntm1 rcntm0 time-out period max node count 0 0 210 ms up to 255 nodes 0 1 52.5 ms up to 64 nodes 1 0 26.25 ms up to 32 nodes 1 1 13.125 ms* up to 16 nodes (note 6.1) note 6.1 the node id value 255 must exist in the network for the 13.125 ms time-out to be valid.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 37 rev. 08-18-03 datasheet 6.3 bus control register the bus control register is new to the com20022i. it is an 8-bit read/write register accessed when the sub address bits subad[2:0] are set up accordingly (see the bit definitions of the sub address register). this register contains bits for control of the dma f unctionality. the drqpol bit is used to set the active polarity of the dreq pin. the tcpol bit is used to set the active polarity of tc pin. the dmamd[0,1] bits select the data transfer mode of the dma, either non-burst, burst, programmable- burst by timer or programmable burst by cycle counter. this transfer mode influences to the timing the dreq pin. the use of the itcen/rtrg bit transfer mode dependent. itcen is the internal terminal counter enable. it is used to select whether the dma is terminated by external tc or by either internal or external tc. itcen is for non-burst or burst mode. rtrg selects the re-trigger mode as either external or internal. it is for the two programmable-burst modes. if rtrg = 0, the deasserted dreq pin is reasserted on the falling edge of the nrefex pin. if rtrg = 1, the deasserted dreq pin is reasserted by the timeout of the internal timer (350 ns or 750 ns, as selected by the gttm bit.) see figure below. rtrg=0 nrefex 350/750ns dreq ndack nwr/nrd rtrg=1 dreq ndack nwr/nrd figure 6.1 - illustration of the effect of rtrg bit on dma timing the use of the tc8/rsyn/gttm bit is also transfer mode dependent. tc8 is bit 8 of the terminal count register. rsyn is the refresh synchronous bit; it is used to select whether the dma is started immediately or after refresh execution. gttm is the gate time bit; it is used to select the gate time of the programmable-burst transfer. tc8 is for non-burst or burst mode. rsyn and gttm are for the two programmable-burst modes. the w16 bit is used to enable/disable the 16 bit access. 6.4 dma count register the dma count register is new to the com20022i. it is an 8-bit read/write register accessed when the sub address bits subad[2:0] are set up accordingly (see the bit definitions of the sub address register). this register contains bits for control of the dma functionality. the tc7-tc0 /tim7-tim0 /cyc7-cyc0 bits have one of three functions depending on the dma transfer mode. tc7-tc0 are for non-burst or burst mode. these are the lower 8 bits of the terminal count setting register (the msb is in the bus control register). the tim7-tim0 bits are for setting the time of the continuous dma transfer in programmable-burst by timer mode. the cyc7-cyc0 bits are for setting the cycle count value of the continuous dma transfer in programmable-burst by cycle mode.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 38 smsc com20022i datasheet table 6.3 - status register bit bit name symbol description 7 receiver inhibited ri this bit, if high, indicates that the receiver is not enabled because either an "enable receive to page fnn" command was never issued, or a packet has been deposited into the ram buffer page fnn as specified by the last "enable receive to page fnn" command. no messages will be received until this command is issued, and once the message has been received, the ri bit is set, thereby inhibiting the receiver. the ri bit is cleared by issuing an "enable receive to page fnn" command. this bit, when set, will cause an interrupt if the corresponding bit of the interrupt mask register (imr) is also set. when this bit is set and another station attempts to send a packet to this station, this station will send a nak. 6,5 (reserved) these bits are undefined. 4 power on reset por this bit, if high, indicates that the com20022i has been reset by either a software reset, a hardware reset, or writing 00h to the node id register. the por bit is cleared by the "clear flags" command. 3 test test this bit is intended for test and diagnostic purposes. it is a logic "0" under normal operating conditions. 2 reconfiguration recon this bit, if high, indicates that the line idle timer has timed out because the rxin pin was idle for 20.5 s. the recon bit is cleared during a "clear flags" command. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. the interrupt service routine should consist of examining the myrecon bit of the diagnostic status register to determine whether there are consecutive reconfigurations caused by this node. 1 transmitter message acknowledged tma this bit, if high, indicates that the packet transmitted as a result of an "enable transmit from page fnn" command has been acknowledged. this bit should only be considered valid after the ta bit (bit 0) is set. broadcast messages are never acknowledged. the tma bit is cleared by issuing the "enable transmit from page fnn" command. 0 transmitter available ta this bit, if high, indicates that the transmitter is available for transmitting. this bit is set when the last byte of scheduled packet has been transmitted out, or upon execution of a "disable transmitter" command. the ta bit is cleared by issuing the "enable transmit from page fnn" command after the node next receives the token. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 39 rev. 08-18-03 datasheet table 6.4 - diagnostic status register bit bit name symbol description 7 my reconfiguration my- recon this bit, if high, indicates that a past reconfiguration was caused by this node. it is set when the lost token timer times out, and should be typically read following an interrupt caused by recon. refer to the improved diagnostics section for further detail. 6 duplicate id dupid this bit, if high, indicates that the value in the node id register matches both destination id characters of the token and a response to this token has occurred. trailing zero's are also verified. a logic "1" on this bit indicates a duplicate node id, thus the user should write a new value into the node id register. this bit is only useful for duplicate id detection when the device is off line, that is, when the transmitter is disabled. when the device is on line this bit will be set every time the device gets the token. this bit is reset automatically upon reading the diagnostic status register. refer to the improved diagnostics section for further detail. 5 receive activity rcvact this bit, if high, indicates that data activity (logic "1") was detected on the rxin pin of the device. refer to the improved diagnostics section for further detail. 4 token seen token this bit, if high, indicates that a token has been seen on the network, sent by a node other than this one. refer to the improved diagnostic section for further detail. 3 excessive nak excnak this bit, if high, indicates that either 128 or 4 negative acknowledgements have occurred in response to the free buffer enquiry. this bit is cleared upon the "por clear flags" command. reading the diagnostic status register does not clear this bit. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. refer to the improved diagnostics section for further detail. 2 tentative id tentid this bit, if high, indicates that a response to a token whose did matches the value in the tentative id register has occurred. the second did and the trailing zero's are not checked. since each node sees every token passed around the network, this feature can be used with the device on- line in order to build and update a network map. refer to the improved diagnostics section for further detail. 1 new next id new nxtid this bit, if high, indicates that the next id register has been updated and that a node has either joined or left the network. reading the diagnostic status register does not clear this bit. this bit, when set, will cause an interrupt if the corresponding bit in the imr is also set. the bit is cleared by reading the next id register. 1,0 (reserved) these bits are undefined.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 40 smsc com20022i datasheet table 6.5 - command register data command description 0000 0000 clear transmit interrupt this command is used only in the command chaining operation. please refer to the command chaining section for definition of this command. 0000 0001 disable transmitter this command will cancel any pending transmit command (transmission that has not yet started) and will set the ta (transmitter available) status bit to logic "1" when the com20022i next receives the token. 0000 0010 disable receiver this command will cancel any pending receive command. if the com20022i is not yet receiving a packet, the ri (receiver inhibited) bit will be set to logic "1" the next time the token is received. if packet reception is already underway, reception will run to its normal conclusion. b0fn n100 enable receive to page fnn this command allows the com20022i to receive data packets into ram buffer page fnn and resets the ri status bit to logic "0". the values placed in the "nn" bits indicate the page that the data will be received into (page 0, 1, 2, or 3). if the value of "f" is a logic "1", an offset of 256 bytes will be added to that page specified in "nn", allowing a finer resolution of the buffer. refer to the selecting ram page size section for further detail. if the value of "b" is logic "1", the device will also receive broadcasts (transmissions to id zero). the ri status bit is set to logic "1" upon successful reception of a message. 00fn n011 enable transmit from page fnn this command prepares the com200 22i to begin a transmit sequence from ram buffer page fnn the next time it receives the token. the values of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3). if "f" is logic "1", an offset of 256 bytes is the start of the page specified in "nn", allowing a finer resolution of the buffer. refer to the selecting ram page size section for further detail. when this command is loaded, the ta and tma bits are reset to logic "0". the ta bit is set to logic "1" upon completion of the transmit sequence. the tma bit will have been set by this time if the device has received an ack from the destination node. the ack is strictly hardware level, sent by the receiving node before its microcontroller is even aware of message reception. refer to figure 3.1 for details of the transmit sequence and its relation to the ta and tma status bits. 0000 c101 define configuration this command defines the maximum length of packets that may be handled by the device. if "c" is a logic "1", the device handles both long and short packets. if "c" is a logic "0", the device handles only short packets. 000r p110 clear flags this command resets certain status bits of the com20022i. a logic "1" on "p" resets the por status bit and the excnak diagnostic status bit. a logic "1" on "r" resets the recon status bit. 0000 1000 clear receive interrupt this command is used only in the command chaining operation. please refer to the command chaining section for definition of this command. 0001 1000 start internal operation this command restarts the stopped internal operation after changing ckup1 or ckup0 bit. 0001 0000 clear mask bit of dmaend this command resets a mask bit of the dmaend. it is for clearing interrupt by dma transfer finished.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 41 rev. 08-18-03 datasheet table 6.6 - address pointer high register bit bit name symbol description 7 read data rddata this bit tells the com20022i whether the following access will be a read or write. a logic "1" prepares the device for a read, a logic "0" prepares it for a write. 6 auto increment autoinc this bit controls whether the address pointer will increment automatically. a logic "1" on this bit allows automatic increment of the pointer after each access, while a logic "0" disables this function. please refer to the sequential access memory section for further detail. 5-4 (reserved) these bits are undefined. 3 dma enable dmaen this bit is used to disable/enable the assertion of the dma request (dreq pin) after writing the address pointer low register. dmaen=0: disable (default). dmaen=1: enable the assertion of the dreq pin after writing the address pointer low register. writing dmaen=0 during the dma operation will negate the dreq pin immediately. the dma operation is terminated immediately after the next dack pin negation. the inverting signal of damen is the interrupt source signal dmaend. the dmaen bit is cleared automatically by finishing the dma. if the dmaend bit in the mask register is not masked, the interrupt occurs by finishing the dma operation. 2-0 address 10-8 a10-a8 these bits hold the upper three address bits which provide addresses to ram.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 42 smsc com20022i datasheet table 6.7 - address pointer low register bit bit name symbol description 7-0 address 7-0 a7-a0 swap these bits hold the lower 8 address bits which provide the addresses to ram. when 16 bit access is enabled, (w16=1), a0 becomes the swap bit. swap bit is undefined after a hardware reset. the swap bit must be set before w16 bit is set to ?1?. the swap bit is used to swap the upper and lower data byte. the swap bit influences both cpu cycle and dma cycle. see table below. detected host interface mode swap bit d15-d8 pin d7-d0 pin intel 80xx mode 0 odd even (rd, wr mode) 1 even odd motorola 68xx mode 0 even odd (dir, ds mode) 1 odd even table 6.8 - sub address register bit bit name symbol description 7-3 reserved these bits are undefined. 2,1,0 sub address 2,1,0 subad 2,1,0 these bits determine which register at address 07 may be accessed. the combinations are as follows: subad2 subad1 subad0 register 0 0 0 tentative id \ (same 0 0 1 node id \ as in 0 1 0 setup 1 / config 0 1 1 next id / register) 1 0 0 setup 2 1 0 1 bus control 1 1 0 dma count 1 1 1 reserved subad1 and subad0 are exactly the same as exist in the configuration register. subad2 is cleared automatically by writing the configuration register.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 43 rev. 08-18-03 datasheet table 6.9 - configuration register bit bit name symbol description 7 reset reset a software reset of the com20022i is executed by writing a logic "1" to this bit. a software reset does not reset the microcontroller interface mode, nor does it affect the configuration register. the only registers that the software reset affect are the status register, the next id register, and the diagnostic status register. this bit must be brought back to logic "0" to release the reset. 6 command chaining enable cchen this bit, if high, enables the command chaining operation of the device. please refer to the command chaining section for further details. a low level on this bit ensures software compatibility with previous smsc arcnet devices. 5 transmit enable txen when low, this bit disables transmissions by keeping npulse1, npulse2 if in non-backplane mode, and ntxen pin inactive. when high, it enables the above signals to be activated during transmissions. this bit defaults low upon reset. this bit is typically enabled once the node id is determined, and never disabled during normal operation. please refer to the improved diagnostics section for details on evaluating network activity. 4,3 extended timeout 1,2 et1, et2 these bits allow the network to operate over longer distances than the default maximum 1 mile by controlling the response, idle, and reconfiguration times. all nodes should be configured with the same timeout values for proper network operation. for the com20022i with a 20 mhz crystal oscillator, the bit combinations follow: et2 0 0 1 1 et1 0 1 0 1 response time ( s) 298.4 149.2 74.7 18.7 idle time ( s) 328 164 82 20.5 reconfig time (ms) 420 420 420 210 note: these values are for 10mbps and rcntmr[1,0]=00. reconfiguration time is changed by the rcntmr1 and rcntmr0 bits. 2 backplane back- plane a logic "1" on this bit puts the device into backplane mode signaling which is used for open drain and differential driver interfaces. 1,0 sub address 1,0 subad 1,0 these bits determine which register at address 07 may be accessed. the combinations are as follows: subad1 subad0 register 0 0 tentative id 0 1 node id 1 0 setup 1 1 1 next id see also the sub address register.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 44 smsc com20022i datasheet table 6.10 - setup 1 register bit bit name symbol description 7 pulse1 mode p1mode this bit determines the type of pulse1 output driver used in backplane mode. when high, a push/pull output is used. when low, an open drain output is used. the default is open drain. 6 four nacks four nacks this bit, when set, will cause the exnack bit in the diagnostic status register to set after four nacks to free buffer enquiry are detected by the com20022i. this bit, when reset, will set the exnack bit after 128 nacks to free buffer enquiry. the default is 128. 5 reserved do not set. 4 receive all rcvall this bit, when set, allows the com20022i to receive all valid data packets on the network, regardless of their destination id. this mode can be used to implement a network monitor with the transmitter on- or off-line. note that acks are only sent for packets received with a destination id equal to the com20022i's programmed node id. this feature can be used to put the com20022i in a 'listen-only' mode, where the transmitter is disabled and the com20022i is not passing tokens. defaults low. 3,2,1 clock prescaler bits 3,2,1 ckp3,2,1 these bits are used to determine the data rate of the com20022i. the following table is for a 20 mhz crystal: (clock multiplier is bypassed) ckp3 0 0 0 0 1 ckp2 0 0 1 1 0 ckp1 0 1 0 1 0 divisor 8 16 32 64 128 speed 2.5mbs 1.25mbs 625kbs 312.5kbs 156.25kbs note: the lowest data rate achievable by the com20022i is 156.25kbs. defaults to 000 or 2.5mbs. for clock multiplier output clock speed greater than 20 mhz, ckp3, ckp2 and ckp1 must all be zero. 0 slow arbitration select slowarb this bit, when set, will divide the arbitration clock by 2. memory cycle times will increase when slow arbitration is selected. note: for clock multiplier output clock speeds greater than 40 mhz, slowarb must be set. defaults to low.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 45 rev. 08-18-03 datasheet table 6.11 - setup 2 register bit bit name symbol description 7 read bus timing select rbustmg this bit is used to disable/enable the high speed cpu read function for high speed cpu bus support. rbustmg=0: disable (default), rbustmg=1: enable. that is, if bustmg (pin 26) = 1 and rbustmg = 1, high speed cpu read operations are enabled. it does not influence write operation. high speed cpu read operation is only for non-multiplexed bus. 6 reserved this bit is undefined. 5,4 clock multiplier ckup1, 0 higher frequency clocks are generated from the 20 mhz crystal through the selection of these two bits as shown. this clock multiplier is powered-down on default. after changing the ckup1 and ckup0 bits, the arcnet core operation is stopped and the internal pll in the clock multiplier is awakened and it starts to generate the 40 mhz. the lock out time of the internal pll is 8 sec typically. after 1 ms it is necessary to write command data '18h' to command register for re-starting the arcnet core operation. ef bit must be ?1? if the data rate is over 5mbps. caution: changing the ckup1 and ckup0 bits must be one time or less after releasing a hardware reset. ckup1 ckup0 clock frequency (data rate) 0 0 20 mhz (up to 2.5mbps) default 0 1 40 mhz (up to 5mbps) 1 0 reserved 1 1 80 mhz (only 10mbps) note: after changing the ckup1 or ckup0 bits, it is necessary to write a command data '18h' to the command register. because after changing the ckup [1, 0] bits, the internal operation is stopped temporarily. the writing of the command is to start the operation. these initializing steps are shown below. 1. hardware reset (power on) 2. change ckup[1, 0] bit 3. wait 1msec (wait until stable oscillation) 4. write command '18h' (start internal operation) 5. start initializing routine (execute existing software) 3 enhanced functions ef this bit is used to enable the new enhanced functions in the com20022i. ef = 0: disable (default), ef = 1: enable. if ef = 0, the timing and function is the same as in the com20020, revision b. see appendix ?a?. ef bit must be ?1? if the data rate is over 5mbps. ef bit should be ?1? for new design customers. ef bit should be ?0? for replacement customers. 2 no synchronous nosync this bit is used to enable the sync command during initialization. nosync= 0, enable (default) the line must be idle for the ram initialization sequence to be written. nosync= 1, disable:) the line does not have to be idle for the ram initialization sequence to be written. see appendix ?a?.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 46 smsc com20022i datasheet bit bit name symbol description 1,0 reconfiguration timer 1, 0 rcntm1,0 these bits are used to program the reconfiguration timer as a function of maximum node count. these bits set the time out period of the reconfiguration timer as shown below. the time out periods shown are for 10 mbps. rcntm1 rcntm0 time out period max node count 0 0 210 ms up to 255 nodes 0 1 52.5 ms up to 64 nodes 1 0 26.25 ms up to 32 nodes 1 1 13.125 ms* up to 16 nodes note*: the node id value 255 must exist in the network for 13.125 ms timeout to be valid. table 6.12 - bus control register bit bit name symbol description 7 16 bit access w16 this bit is used to disable/enable the 16 bit access. it influences both cpu cycle and dma cycle. w16= 0: disable (default); w16= 1: enable 6 reserved this bit is undefined. 5 internal terminal counter enable; re-trigger mode itcen/ rtrg the function of this bit is mode dependent. itcen is for non-burst or burst mode. rtrg is for the two programmable-burst modes. itcen = 0: terminate the dma only by external tc. itcen = 1: terminate the dma by internal or external tc. rtrg = 0: external re-trigger mode; negated dreq pin is re- asserted by falling edge of nrefex pin. rtrg = 1: internal re- trigger mode; negated dreq pin is re-asserted by timeout of internal gate timer (350ns/750ns). 4 terminal count bit 8 refresh synchronous gate time tc8/ rsyn/ gttm the function of this bit is mode dependent. tc8 is for non-burst or burst mode. rsyn and gttm are for the two programmable-burst modes. rsyn is for external re-trigger mode. gttm is for internal re-trigger mode. non-burst or burst mode: tc8: bit 8 (msb) of 9 bit terminal count setting register. the other 8 bits are in the dma count register. terminal count setting register is ignored when itcen = 0. programmable-burst and external re-trigger mode: rsyn = 0: dma is started immediately. rsyn = 1: dma is started after refresh execution. programmable-burst and internal re-trigger mode: gttm = 0: gate time is 350ns (min) gttm = 1: gate time is 750ns (min) 3,2 dma transfer mode dmamd1,d mamd0 these bits select the data transfer mode of the dma. these transfer modes influence the timing of asserting/negating the dreq pin. dmamd1 dmamd0 transfer mode 0 0 non-burst (default) 0 1 burst 1 0 programmable-burst by timer 1 1 programmable-burst by cycle counter 1 tc polarity tcpol this bit sets the active polarity of tc pin. tcpol = 0: active high (default), tcpol = 1 active low 0 dreq polarity drqpol this bit sets the active polarity of dreq pin. drqpol = 0: active high (default), drqpol = 1 active low
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 47 rev. 08-18-03 datasheet table 6.13 - dma count register bit bit name symbol description 7-0 terminal count timer mode cycle mode tc7-tc0 tim7-tim0 cyc7-cyc0 tc7-tc0: used for non-burst or burst mode. these are the lower 8 bits of the terminal count setting register. the msb (tc8) is in the bus control register. the terminal count setting range is from 1 to 512 counts (tc8 - tc0 all zeroes means 512 counts). tim7-tim0: used for programmable-burst by timer mode. these bits are for setting the term of the continuous dma transfer. the time range is from 100ns to 25.6 s. the step is 100ns (tim7-tim0 all zeroes means 25.6 s). cyc7-cyc0: used for programmable-burst by cycle mode. these bits are for setting the term of the continuous dma transfer. the cycle range is from 2 to 256 cycles. cyc7-cyc0 all zeroes means 256 cycles. (1 is illegal) address pointer register low 2k x 8 ram 11 data register 8 i/o address 04h i/o address 03h 11-bit counter memory address bus memory data bus d0-d7 high i/o address 02h internal figure 6.2 - sequential access operation
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 48 smsc com20022i datasheet 6.5 internal ram the integration of the 2k x 8 ram in the com20022i represents significant real estate savings. the most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of ram). in addition, the pc board is now free of the cumbersome external ram, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the ram. the integration of ram represents significant cost savings because it isolates the system designer from the changing costs of external ram and it minimizes reliability problems, assembly time and costs, and layout complexity. 6.5.1 sequential access memory the internal ram is accessed via a pointer-based scheme. rather than interfering with system memory, the internal ram is indirectly accessed through the address high and low pointer registers. the data is channeled to and from the microcontroller via the 8-bit data register. for example: a packet in the internal ram buffer is read by the microcontroller by writing the corresponding address into the address pointer high and low registers (offsets 02h and 03h). note that the high register should be written first, followed by the low register, because writing to the low register loads the address. at this point the device accesses that location and places the corresponding data into the data register. the microcontroller then reads the data register (offset 04h) to obtain the data at the specified location. if the auto increment bit is set to logic "1", the device will automatically increment the address and place the next byte of data into the data register, again to be read by the microcontroller. this process is continued until the entire packet is read out of ram. refer to figure 5.6 for an illustration of the sequential access operation. when switching between reads and writes, the pointer must first be written with the starting address. at least one cycle time should separate the pointer being loaded and the first read (see timing parameters). 6.5.2 access speed the com20022i is able to accommodate very fast access cycles to its registers and buffers. arbitration to the buffer does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and stored in a temporary register. likewise, data to be written is stored in the temporary register and then written to memory. for systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the setup1 register equal to logic "1". since the slow arbitration feature divides the input clock by two, the duty cycle of the input clock may be relaxed. 6.6 software interface the microcontroller interfaces to the com20022i via software by accessing the various registers. these actions are described in the internal registers section. the software flow for accessing the data buffer is based on the sequential access scheme. the basic sequence is as follows: disable interrupts write to pointer register high (specifying auto-increment mode) write to pointer register low (this loads the address) enable interrupts read or write the data register (repeat as many times as necessary to empty or fill the buffer) the pointer may now be read to determine how many transfers were completed.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 49 rev. 08-18-03 datasheet the software flow for controlling the configuration, node id, tentative id, and next id registers is generally limited to the initialization sequence and the maintenance of the network map. additionally, it is necessary to understand the details of how the other internal registers are used in the transmit and receive sequences and to know how the internal ram buffer is properly set up. the sequence of events that tie these actions together is discussed as follows. 6.6.1 selecting ram page size during normal operation, the 2k x 8 of ram is divided into four pages of 512 bytes each. the page to be used is specified in the "enable transmit (receive) from (to) page fnn" command, where "nn" specifies page 0, 1, 2, or 3. this allows the user to have constant control over the allocation of ram. when the offset bit "f" (bit 5 of the "enable transmit (receive) from (to) page fnn" command word) is set to logic "1", an offset of 256 bytes is added to the page specified. for example: to transmit from the second half of page 0, the command "enable transmit from page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the command register. this allows a finer resolution of the buffer pages without affecting software compatibility. this scheme is useful for applications which frequently use packet sizes of 256 bytes or less, especially for microcontroller systems with limited memory capacity. the remaining portions of the buffer pages which are not allocated for current transmit or receive packets may be used as temporary storage for previous network data, packets to be sent later, or as extra memory for the system, which may be indirectly accessed. if the device is configured to handle both long and short packets (see "define configuration" command), then receive pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. in this case, the transmit pages may be made 256 bytes long, leaving at least 512 bytes free at any given time. even if the command chaining operation is being used, 512 bytes is still guaranteed to be free because command chaining only requires two pages for transmit and two for receive (in this case, two 256 byte pages for transmit and two 512 byte pages for receive, leaving 512 bytes free). please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. the com20022i does not check page boundaries during reception. if the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1kbyte at any given time. even if the command chaining operation is being us ed, 1kbyte is still guaranteed to be free because command chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1k free). the general rule which may be applied to determine where in ram a page begins is as follows: address = (nn x 512) + (f x 256).
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 50 smsc com20022i datasheet sid did count = 256-n not used data byte 1 data byte 2 data byte n-1 data byte n not used sid did 0 count = 512-n not used data byte 1 data byte 2 data byte n-1 data byte n short packet format long packet format a ddress address 0 1 2 count 255 511 n = data packet length sid = source id did = destination id (did = 0 for broadcasts) 0 1 2 count 511 3 figure 6.3 - ram buffer packet configuration 6.6.2 transmit sequence during a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the ram buffer and writes into it. the appropriate buffer size is specified in the "define configuration" command. when long packets are enabled, the com20022i interprets the packet as either a long or short packet, depending on whether the buffer address 2 contains a zero or non-zero value. the format of the buffer is shown in figure 5.7 address 0 contains the source identifier (s id); address 1 contains the destination identifier (did); address 2 (count) contains, for short packets, the value 256-n, where n represents the number of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long packet. in the latter case, address 3 (count) would contain the value 512-n, where n represents the number of information bytes in the message. the sid in address 0 is used by the receiving node to reply to the transmitting node. the com20022i puts the local id in this location, therefore it is not necessary to write into this location. please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes. a minimum value of 257 exists on a long packet so that the count is expressible in eight bits . this leaves three exception packet lengths which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. if packets of these lengths must be sent, the user must add dummy bytes to the packet in order to make the packet fit into a long packet. once the packet is written into the buffer, the microcontroller awaits a logic "1" on the ta bit, indicating that a previous transmit command has concluded and anothe r may be issued. each time the message is loaded and a transmit command issued, it will take a variable amount of time before the message is transmitted, depending on the traffic on the network and the location of the token at the time the transmit command was issued. the conclusion of the transmit command will generate an interrupt if the interrupt mask allows it. if the device is configured for the command chaining operation, please see the command chaining section for further detail on the transmit sequence. once the ta bit becomes a logic "1", the microcontroller may issue the "enable transmit from page fnn" command, which resets the ta and tma bits to logic "0". if the
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 51 rev. 08-18-03 datasheet message is not a broadcast, the com20022i automatically sends a free buffer enquiry to the destination node in order to send the message. at this point, one of four possibilities may occur. the first possibility is if a free buffer is available at the destination node, in which case it responds with an acknowledgement. at this point, the com20022i fetches the data from the transmit buffer and performs the transmit sequence. if a successful transmit sequence is completed, the tma bit and the ta bit are set to logic "1". if the packet was not transmitted successf ully, tma will not be set. a successful transmission occurs when the receiving node responds to the packet with an ack. an unsuccessful transmission occurs when the receiving node does not respond to the packet. the second possibility is if the destination node responds to the free buffer enquiry with a negative acknowledgement. a nak occurs when the ri bit of the destination node is a logic "1". in this case, the token is passed on from the transmitting node to the next node. the next time the transmitter receives the token, it will again transmit a free buffer enquiry. if a nak is again received, the token is again passed onto the next node. the excessive nak bit of the diagnostic status register is used to prevent an endless sending of fbe's and nak's. if no limit of fbe-nak sequences existed, the transmitting node would continue issuing a free buffer enquiry, even though it would continuously receive a nak as a response. the excnak bit generates an interrupt (if enabled) in order to tell the microcontroller to disable the transmitter via the "disable transmitter" command. this causes the transmission to be abandoned and the ta bit to be set to a logic "1" when the node next receives the token, while the tma bit remains at a logic "0". please refer to the improved diagnostics section for further detail on the excnak bit. the third possibility which may occur after a free buffer enquiry is issued is if the destination node does not respond at all. in this case, the ta bit is set to a logic "1", while the tma bit remains at a logic "0". the user should determine whether the node should try to reissue the transmit command. the fourth possibility is if a non-traditional response is received (some pattern other than ack or nak, such as noise). in this case, the token is not passed onto the next node, which causes the lost token timer of the next node to time out, thus generating a network reconfiguration. the "disable transmitter" command may be used to cancel any pending transmit command when the com20022i next receives the token. normally, in an active network, this command will set the ta status bit to a logic "1" when the token is received. if the "disable transmitter" command does not cause the ta bit to be set in the time it takes the token to make a round trip through the network, one of three situations exists. either the node is disconnected from the network, or there are no other nodes on the network, or the external receive circuitry has failed. these situations can be determined by either using the improved diagnostic features of the com20022i or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message. 6.6.3 receive sequence a receive sequence begins with the ri status bit becoming a logic "1", which indicates that a previous reception has concluded. the microcontroller will be inte rrupted if the corresponding bit in the interrupt mask register is set to logic "1". otherwise, the microcontroller must periodically check the status register. once the microcontroller is alerted to the fact that the previous reception has concluded, it may issue the "enable receive to page fnn" command, which resets the ri bit to logic "0" and selects a new page in the ram buffer. again, the appropriate buffer size is specified in the "define configuration" command. typically, the page which just received the data packet will be read by the microcontroller at this point. once the "enable receive to page fnn" command is issued, the microcontroller attends to other duties. there is no way of knowing how long the new reception will take, since another node may transmit a packet at any time. when another node does transmit a packet to this node, and if the "define configuration" command has enabled the reception of long packets, the com20022i interprets the packet as either a long or short packet, depending on whether the content of the buffer location 2 is zero or non-zero. the format of the buffer is shown in figure 5.7. address 0 contains the source identifier (sid), address 1 contains the destination identifier (did), and address 2 contains, for short packets, the value 256-n, where n represents the message length, or for long packets, the value 0, indicating that it is indeed a long packet. in the latter case, address 3 contains the value 512-n, where n represents the message length. note that on reception,
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 52 smsc com20022i datasheet the com20022i deposits packets into the ram buffer in the same format that the transmitting node arranges them, which allows for a message to be received and then retransmitted without rearranging any bytes in the ram buffer other than the sid and did. once the packet is received and stored correctly in the selected buffer, the com20022i sets the ri bit to logic "1" to si gnal the microcontroller that the reception is complete. figure 6.4 - command chaining status register queue 6.7 command chaining the command chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention. through the use of a dual two-level fifo, commands to be transmitted and received, as well as the status bits, are pipelined. in order for the com20022i to be compatible with previous smsc arcnet device drivers, the device defaults to the non-chaining mode. in order to take advantage of the command chaining operation, the command chaining mode must be enabled via a logic "1" on bit 6 of the configuration register. in command chaining, the status register appears as in figure 6.4. the following is a list of command chaining guidelines for the software programmer. further detail can be found in the transmit command chaining and receive command chaining sections. the device is designed such that the interrupt serv ice routine latency does not affect performance. up to two outstanding transmissions and two outstanding receptions can be pending at any given time. the commands may be given in any order. up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the device, along with their respective status bits. the interrupt mask bits act on tta (rising transition on transmitter available) for transmit operations and tri (rising transition of receiver inhibited) for receive operations. tta is set upon completion of a packet transmission only. tri is set upon completion of a packet reception only. typically there is no need to mask the tta and tri bits after clearing the interrupt. the traditional ta and ri bits are still available to reflect the present status of the device. 6.7.1 transmit command chaining when the processor issues the first "enable transmit to page fnn" command, the com20022i responds in the usual manner by resetting the ta and tma bits to prepare for the transmission from the specified page. the ta bit can be used to see if there is currently a transmission pending, but the ta bit is really meant to be used in the non-chaining mode only. the tta bits provide the relevant information for the device in the command chaining mode. in the command chaining mode, at any time after the first command is issued, the processor can issue a second "enable transmit from page fnn" command. the com20022i stores the fact that the second transmit command was issued, along with the page number. tri ri ta por test recon tma tta tma tta tri msb lsb
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 53 rev. 08-18-03 datasheet after the first transmission is completed, the com20022i updates the status register by setting the tta bit, which generates an interrupt. the interrupt service routine should read the status register. at this point, the tta bit will be found to be a logic "1" and the tma (transmit message acknowledge) bit will tell the processor whether the transmission was successful. after reading the status register, the "clear transmit interrupt" command is issued, thus resetting the tta bit and clearing the interrupt. note that only the "clear transmit interrupt" command will clear the tta bit and the interrupt. it is not necessary, however, to clear the bit or the interrupt right away because the status of the transmit operation is double buffered in order to retain the results of the first transmission for analysis by the processor. this information will remain in the status register until the "clear transmit interrupt" command is issued. note that the interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is acknowledged. the com20022i guarantees a minimum of 200ns (at ef=1) interrupt inactive time interval between interrupts. the tma bit is also double buffered to reflect whether the appropriate transmission was a success. the tma bit should only be considered valid after the corresponding tta bit has been set to a logic "1". the tma bit never causes an interrupt. when the token is received again, the second transmission will be automatically initiated after the first is completed by using the stored "enable transmit from page fnn" command. the operation is as if a new "enable transmit from page fnn" command has just been issued. after the first transmit status bits are cleared, the status register will again be updated with the results of the second transmission and a second interrupt resulting from the second transmission will occur. the com20022i guarantees a minimum of 200ns (at ef=1) interrupt inactive time interval before the following edge. the transmitter available (ta) bit of the interrupt mask register now masks only the tta bit of the status register, not the ta bit as in the non-chaining mode. since the tta bit is only set upon transmission of a packet (not by reset), and since the tta bit may easily be reset by issuing a "clear transmit interrupt" command, there is no need to use the ta bit of the interrupt mask register to mask interrupts generated by the tta bit of the status register. in command chaining mode, the "disable transmitter" command will cancel the oldest transmission. this permits canceling a packet destined for a node not ready to receive. if both packets should be canceled, two "disable transmitter" commands should be issued. 6.7.2 receive command chaining like the transmit command chaining operation, the processor can issue two consecutive "enable receive from page fnn" commands. after the first packet is received into the first specified page, the tri bit of the status register will be set to logic "1", causing an interrupt. again, the interrupt need not be serviced immediately. typically, the interrupt service routine will read the status register. at this point, the ri bit will be found to be a logic "1". after reading the status register, the "clear receive interrupt" command should be issued, thus resetting the tri bit and clearing the interrupt. note that only the "clear receive interrupt" command will clear the tri bit and the interrupt. it is not necessary, however, to clear the bit or the interrupt right away because the status of the receive operation is double buffered in order to retain the results of the first reception for analysis by the processor, therefore the information will remain in the status register until the "clear receive interrupt" command is issued. note that the interrupt will remain active until the "clear receive interrupt" command is issued, and the second interrupt will be stored until the first interrupt is acknowledged. a minimum of 200ns (at ef=1) interrupt inactive time interval between interrupts is guaranteed. the second reception will occur as soon as a second packet is sent to the node, as long as the second "enable receive to page fnn" command was issued. the operation is as if a new "enable receive to page fnn" command has just been issued. after the first receive status bits are cleared, the status register will again be updated with the results of the second reception and a second interrupt resulting from the second reception will occur. in the com20022i, the receive inhibit (ri) bit of the interrupt mask regi ster now masks only the tri bit of the status register, not the ri bit as in the non-chaining mode. since the tri bit is only set upon
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 54 smsc com20022i datasheet reception of a packet (not by reset), and since the tri bit may easily be reset by issuing a "clear receive interrupt" command, there is no need to use the ri bit of the interrupt mask register to mask interrupts generated by the tri bit of the status register. in command chaining mode, the "disable receiver" command will cancel the oldest reception, unless the reception has already begun. if both receptions should be canceled, two "disable receiver" commands should be issued. 6.8 reset details 6.8.1 internal reset logic the com20022i includes special reset circuitry to guarantee smooth operation during reset. special care is taken to assure proper operation in a variety of systems and modes of operation. the com20022i contains digital filter circuitry and a schmitt trigger on the nreset signal to reject glitches in order to ensure fault-free operation. the com20022i supports two reset options; software and hardware reset. a software reset is generated when a logic "1" is written to bit 7 of the configuration register. the device remains in reset as long as this bit is set. the software reset does not affect the microcontroller interface modes determined after hardware reset, nor does it affect the contents of the address pointer registers, the configuration register, or the setup1 register. a hardware reset occurs when a low signal is asserted on the nreset input. the minimum reset pulse width is 5t xtl. this pulse width is used by the internal digital filter, which filters short glitches to allow only valid resets to occur. upon reset, the transmitter portion of the device is disabled and the internal registers assume those states outlined in the internal registers section. after the nreset signal is removed the user may write to the internal registers. since writing a non-zero value to the node id register wakes up the com20022i core, the setup1 register should be written before the node id register. once the node id register is written to, the com20022i reads the value and executes two write cycles to the ram buffer. address 0 is written with the data d1h and address 1 is written with the node id. the data pattern d1h was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation. 6.9 initialization sequence 6.9.1 bus determination writing to and reading from an odd address location from the com20022i's address space causes the com20022i to determine the appropriate bus interface. when the com20022i is powered on the internal registers may be written to. since writing a non-zero value to the node id register wakes up the core, the setup1 register should be written to before the node id register. until a non-zero value is placed into the nid register, no microcode is executed, no tokens are passed by this node, and no reconfigurations are generated by this node. once a non-zero value is placed in the register, the core wakes up, but the node will not attempt to join the network until the tx enable bit of the configuration register is set. before setting the tx enable bit, the software may make some determinations. the software may first observe the receive activity and the token seen bits of the diagnostic status register to verify the health of the receiver and the network. next, the uniqueness of the node id value placed in the node id register is determined. the tx enable bit should still be a logic "0" until it is ensured that the node id is unique. if this node id already exists, the duplicate id bit of the diagnostic status register is set after a maximum of 210ms (or 420ms if the et1 and et2 bits are other than 1,1). to determine if another node on the network already has this id, the com20022i compares the value in the node id register with the did's of the token, and determines whether there is a response to it. once the diagnostic status register is read, the dupid bit is cleared.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 55 rev. 08-18-03 datasheet the user may then attempt a new id value, wait 210ms before checking the duplicate id bit, and repeat the process until a unique node id is found. at this point, the tx enable bit may be set to allow the node to join the network. once the node joins the network, a reconfiguration occurs, as usual, thus setting the myrecon bit of the diagnostic status register. the tentative id register may be used to build a network map of all the nodes on the network, even once the com20022i has joined the network. once a value is placed in the tentative id register, the com20022i looks for a response to a token whose did matches the tentative id register. the software can record this information and continue placing tentative id values into the register to continue building the network map. a complete network map is only valid until nodes are added to or deleted from the network. note that a node cannot detect the existence of the next logical node on the network when using the tentative id. to determine the next logical node, the software should read the next id register. 6.10 improved diagnostics the com20022i allows the user to better manage the operation of the network through the use of the internal diagnostic status register. a high level on the my reconfiguration (myrecon) bit indicates that the token reception timer of this node expired, causing a reconfiguration by this node. after the reconfiguration (recon) bit of the status register interrupts the microcontroller, the interrupt service routine will typically read the myrecon bit of the diagnostic status register. reading the diagnostic status register resets the myrecon bit. successive occurrences of a logic "1" on the myrecon bit indicates that a problem exists with this node. at that point, the transmitter should be disabled so that the entire network is not held down while the node is being evaluated. the duplicate id (dupid) bit is used before the node joins the network to ensure that another node with the same id does not exist on the network. once it is determined that the id in the node id register is unique, the software should write a logic "1" to bit 5 of the configuration register to enable the basic transmit function. this allows the node to join the network. the receive activity (rcvact) bit of the diagnostic status register will be set to a logic "1" whenever activity (logic "1") is detected on the rxin pin. the token seen (token) bit is set to a logic "1" whenever any token has been seen on the network (except those tokens transmitted by this node). the rcvact and token bits may help the user to troubleshoot the network or the node. if unusual events are occurring on the network, the user may find it valuable to use the txen bit of the configuration register to qualify events. different combinations of the rcvact, token, and txen bits, as shown indicate different situations: 6.10.1 normal results: rcvact=1, token=1, txen=0: the node is not part of the network. the network is operating properly without this node. rcvact=1, token=1, txen=1: the node sees receive activity and sees the token. the basic transmit function is enabled. network and node are operating properly. myrecon=0, dupid=0, rcvact=1, txen=0, token=1: single node network.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 56 smsc com20022i datasheet 6.10.2 abnormal results: rcvact=1, token=0, txen=x: the node sees receive activity, but does not see the token. either no other nodes exist on the network, some type of data corru ption exists, the media driver is malfunctioning, the topology is set up incorrectly, there is noise on the network, or a reconfiguration is occurring. rcvact=0, token=0, txen=1: no receive activity is seen and the basic transmit function is enabled. the transmitter and/or receiver are not functioning properly. rcvact=0, token=0, txen=0: no receive activity and basic transmit function disabled. this node is not connected to the network. the excessive nak (excnak) bit is used to replace a timeout function traditionally implemented in software. this function is necessary to limit the number of times a sender issues a fbe to a node with no available buffer. when the destination node replies to 128 fbes with 128 naks or 4 fbes with 4 naks, the excnak bit of the sender is set, generating an interrupt. at this point the software may abandon the transmission via the "disable transmitter" command. this sets the ta bit to logic "1" when the node next receives the token, to allow a different transmission to occur. the timeout value for the exnack bit (128 or 4) is determined by the four-naks bit on the setup1 register. the user may choose to wait for more nak's before disabling the transmitter by taking advantage of the wraparound counter of the excnak bit. when the excnak bit goes high, indicating 128 or 4 naks, the "por clear flags" command may be issued to reset the bit so that it will go high again after another count of 128 or 4. the software may count the number of times the excnak bit goes high, and once the final count is reached, the "disable transmitter" command may be issued. the new next id bit permits the software to detect the withdrawal or addition of nodes to the network. the tentative id bit allows the user to build a network map of those nodes existing on the network. this feature is useful because it minimizes the need for human intervention. when a value placed in the tentative id register matches the node id of another node on the network, the tentid bit is set, telling the software that this node id already exists on the network. the software should periodically place values in the tentative id register and monitor the new next id bit to maintain an updated network map. 6.11 oscillator the com20022i contains circuitry which, in conjunction with an external parallel resonant crystal or ttl clock, forms an oscillator. if an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). no external resistor is required, since the com20022i contains an internal resistor. the crystal must have an accuracy of 0.020% or better. the oscillation frequency range is from 10 mhz to 20 mhz. the crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. the oscillation frequency must be 20mhz when the internal clock multiplier is turned on. the xtal2 side of the crystal may be loaded with a single 74hc-type buffer in order to generate a clock for other devices. the user may attach an external ttl clock, rather than a crystal, to the xtal1 signal. in this case, a 390 ? pull-up resistor is required on xtal1, while xtal2 should be left unconnected.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 57 rev. 08-18-03 datasheet chapter 7 operational description 7.1 maximum guaranteed ratings* operating temperature range ............................................................................................... -40 o c to +85 o c storage temperatur e range ................................................................................................-55 o c to +150 o c lead temperature (soldering, 10 seconds) ....................................................................................... +325 o c positive voltage on any pin, with respect to ground ........................................................................v dd +0.3v negative voltage on any pin, with respect to ground ............................................................................ . -0.3v maximum v dd .............................................................................................................................. ............ +7v *stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes or "glitches" on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists it is suggested that a clamp circuit be used. 7.2 dc electrical characteristics v dd =5.0v10% com20022i: t a =0 o c to +70 o c, com20022ii: t a =-40 o c to +85 o c parameter symbol min typ max unit comment low input voltage 1 (all inputs except a2, xtal1, nreset, nrd, nwr, nrefex and rxin) high input voltage 1 (all inputs except a2, xtal1, nreset, nrd, nwr, nrefex and rxin) v il1 v ih1 2.0 0.8 v v ttl levels ttl levels low input voltage 2 (xtal1) high input voltage 2 (xtal1) v il2 v ih2 4.0 1.0 v v ttl clock input
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 58 smsc com20022i datasheet parameter symbol min typ max unit comment low to high threshold input voltage (a2, nreset, nrd, nwr, nrefex and rxin) high to low threshold input voltage (a2, nreset, nrd, nwr, nrefex and rxin) v ilh v ihl 1.8 1.2 v v schmitt trigger, all values at v dd = 5v low output voltage 1 (npulse1 in push/pull mode, npulse2, ntxen, dreq, niocs16) high output voltage 1 (npulse1 in push/pull mode, npulse2, ntxen, dreq, niocs16) v ol1 v oh1 v oh1c 2.4 0.8 x v dd 0.4 v v i sink =4ma i source =-2ma i source =-200a (except dreq, niocs16) low output voltage 2 (d0-d15) high output voltage 2 (d0-d15) v ol2 v oh2 2.4 0.4 v v i sink =16ma i source =-12ma low output voltage 3 (nintr) high output voltage 3 (nintr) v ol3 v oh3 2.4 0.8 v v i sink =24ma i source =-10ma low output voltage 4 (npulse1 in open-drain mode) v ol4 0.5 v i sink =48ma open drain driver dynamic v dd supply current i dd1 i dd2 tbd tbd ma ma 5 mbps 10 mbps all outputs open input pull-up current (npulse1 in open-drain mode, a1, ad0-ad2, d3-d15, nrefex, (ndack and tc in bustmg = h)) input leakage current (all inputs except a1, ad0-ad2, d3-d15, xtal1, xtal2, nrefex, (ndack and tc in bustmg = h)) i p i l 80 200 10 a a v in =0.0v v ss < v in < v dd
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 59 rev. 08-18-03 datasheet capacitance (t a = 25c; f c = 1mhz; v dd = 0v) output and i/o pins capacitive load specified as follows: parameter symbol min typ max unit comment input capacitance c in 5.0 pf output capacitance 1 (all outputs except xtal2, npulse1 in push/pull mode) output capacitance 2 (npulse1, in backplane mode only - open drain) c out1 c out2 45 400 pf pf maximum capacitive load which can be supported by each output. 0.4v ac measurements are taken at the following points: inputs: 2.4v 1.4v 50% 50% 0.4v 2.4v 1.4v 0.8v outputs: 2.0v 0.8v 2.0v inputs are driven at 2.4v for logic "1" and 0.4 v for logic "0" except xtal1 pin. outputs are measured at 2.0v min. for logic "1" and 0.8v max. for logic "0". t t t t
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 60 smsc com20022i datasheet chapter 8 timing diagrams figure 8.1 - multiplexed bus, 68xx-like control signals; read cycle ad0-ad2, valid ncs t1 t3 t8 ale valid data t2, t6 t5 t4 t7 d3-d15 dir t9 t10 nds t11 t12 t13 t14 note 2 niocs16 previous value invalid valid value t15 t16 parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nds low nds low to valid data nds high to data high impedance cycle time (nds low to next time low) dir setup to nds active dir hold from nds inactive ale high width ale low width nds low width nds high width niocs16 hold delay from ale low niocs16 output delay from ale low 20 10 10 10 15 0 4t arb * 10 10 20 20 60 20 0 40 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns must be: bustmg pin = high and rbustmg bit = 0 40 t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. note 2 is applied to an access to data register by dma transfer.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 61 rev. 08-18-03 datasheet figure 8.2 - multiplexed bus, 80xx-like control signals; read cycle ale high width ale low width nrd low width nrd high width nwr to nrd low niocs16 hold delay from ale low niocs16 output delay from ale low ad0-ad2, valid ncs t1 t3 t8 ale valid data t2, t6 t5 t4 t7 d3-d15 nrd t9 t10 nwr t13 t11 t12 niocs16 previous value invalid valid value t15 t14 note 3 note 2 parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nrd low nrd low to valid data nrd high to data high impedance cycle time (nrd low to next time low) 20 10 10 10 15 0 4t arb * 40 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns must be: bustmg pin = high and rbustmg bit = 0 20 20 60 20 20 0 40 the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of the next nrd. notes 2 and 3 are applied to an access to data register by dma transfer. note 3: read cycle for address pointer low/high registers occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of nrd.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 62 smsc com20022i datasheet figure 8.3 - multiplexed bus, 68xx-like control signals write cycle ad0-ad2, valid ncs t1 t3 t8 ale valid data t2, t6 t5 t4 t7 d3-d15 dir t9 t10 note 2 t8** nds t11 t12 t13 t14 t16 niocs16 previous value invalid valid value t15 parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 20 10 10 10 15 10 4t arb * 10 10 20 20 20 20 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nds low valid data setup to nds high data hold from nds high dir setup to nds active dir hold from nds inactive 30 must be: bustmg pin = high ale high width ale low width nds low width nds high width niocs16 hold delay from ale low niocs16 output delay from ale low cycle time (nds to next )** 40 the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: any cycle occurring after a write to address pointer low register requires a minimum of 4t arb from the trailing edge of nds to the leading edge of the next nds. note 2: ** t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits write cycle for address pointer low register occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. note 2 is applied to an access to data register by dma transfer.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 63 rev. 08-18-03 datasheet figure 8.4 - multiplexed bus, 80xx-like control signals; write cycle a d0-ad2, valid ncs t1 t3 ale valid data t2, t6 t5 t4 t7 d3-d15 note 2 t8** nwr t9 t10 nrd t13 t11 t12 t8 niocs16 previous value invalid valid value t14 note 3 t15 parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 20 10 10 10 15 10 4t arb * 20 20 20 20 20 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address setup to ale low address hold from ale low ncs setup to ale low ncs hold from ale low ale low to nds low valid data setup to nds high data hold from nds high 30 ale high width ale low width nwr low width nwr high width nrd to nwr low niocs16 hold delay from ale low niocs16 output delay from ale low cycle time (nwr to next )** must be: bustmg pin = high 40 t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: any cycle occurring after a write to address pointer low register requires a minimum of 4t arb from the trailing edge of nwr to the leading edge of the next nwr. note 2: ** write cycle for address pointer low register occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of the next nwr. notes 2 and 3 are applied to an access to data register by dma transfer. note 3: write cycle for address pointer low register occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of nwr.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 64 smsc com20022i datasheet figure 8.5 - non-multiplexed bus, 80xx-like control signals; read cycle a0-a2 valid data valid d0-d15 ncs t6 t1 t7 t3 t5 t4 t2 nrd nwr t10 t8 t9 note 3 niocs16 t11 valid value t12 note 2 parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 15 10 5** 0 ns ns ns ns ns ns address setup to nrd active address hold from nrd inactive ncs setup to nrd active ncs hold from nrd inactive cycle time (nrd low to next time low) nrd low to valid data nrd high to data high impedance 4t arb * 0 60 20 20 40** 20 ns ns ns ns ns ns case 1: bustmg pin = high and rbustmg bit = 0 nrd low width nrd high width nwr to nrd low niocs16 output delay from ncs low niocs16 hold delay from ncs high 0**** 40*** the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits ncs may become active after control becomes active, but the access time (t6) will now be 45ns measured from the leading edge of ncs. ** t11 is measured from the latest active (valid) timing among ncs, a0-a2. *** t12 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. **** note 2: read cycle for address pointer low/high registers occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of the next nrd. notes 2 and 3 are applied to an access to data register by dma transfer. note 3: read cycle for address pointer low/high registers occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of nrd.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 65 rev. 08-18-03 datasheet figure 8.6 - non-multiplexed bus, 80xx-like control signals; read cycle a0-a2 valid data valid d0-d15 ncs t6 t1 t7 t3 t5 t4 t2 nrd nwr t10 t8 t9 niocs16 t11 valid value t12 note 3 note 2 parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 -5 0 -5 0 ns ns ns ns ns ns address setup to nrd active address hold from nrd inactive ncs setup to nrd active ncs hold from nrd inactive cycle time (nrd low to next time low) nrd low to valid data nrd high to data high impedance 4t arb *+30 0 100 30 20 60** 20 ns ns ns ns ns ns nrd low width nrd high width nwr to nrd low niocs16 output delay from ncs low niocs16 hold delay from ncs high case 2: bustmg pin = low or rbustmg bit = 1 0**** 40*** the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: t6 is measured from the latest active (valid) timing among ncs, nrd, a0-a2. ** t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits note 2: read cycle for address pointer low/high registers occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of the next nrd. notes 2 and 3 are applied to an access to data register by dma transfer. note 3: read cycle for address pointer low/high registers occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of nrd. t11 is measured from the latest active (valid) timing among ncs, a0-a2. *** t12 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. ****
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 66 smsc com20022i datasheet a0-a2 valid data valid d0-d15 ncs t8 t1 t9 t3 t6 t4 t2 nds dir t5 t7 t10 t11 niocs16 t12 valid value t13 note 2 parameter min max units t1 t2 t3 t4 t5 t6 t7 15 10 5** 0 ns address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds low to next time low) dir hold from nds inactive 4t arb * ns ns ns ns ns ns t8 ns nds low to valid data 40** t9 t10 t11 t12 t13 ns ns ns ns ns nds high to data high impedence nds low width nds high width niocs16 output delay from ncs low niocs16 hold delay from ncs high 20 10 10 0 60 20 case 1: bustmg pin = high and rbustmg bit = 0 0**** 40*** the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: ncs may become active after control becomes active, but the access time (t8) will now be 45ns measured from the leading edge of ncs. ** *** t12 is measured from the latest active (valid) timing among ncs, a0-a2. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits t13 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. **** note 2: read cycle for address pointer low/high registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. note 2 is applied to an access to data register by dma transfer. figure 8.7 - non-multiplexed bus, 68xx-like control signals; read cycle
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 67 rev. 08-18-03 datasheet figure 8.8 - non-multiplexed bus, 68xx-like control signals; read cycle a0-a2 valid data valid d0-d15 ncs t8 t1 t9 t3 t6 t4 t2 nds dir t5 t7 t10 t11 niocs16 t12 valid value t13 note 2 parameter min max units t1 t2 t3 t4 t5 t6 t7 -5 0 -5 0 ns address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds low to next time low) dir hold from nds inactive 4t arb *+30 ns ns ns ns ns ns t8 ns nds low to valid data 60** t9 t10 t11 t12 t13 ns ns ns ns ns nds high to data high impedence nds low width nds high width niocs16 output delay from ncs low niocs16 hold delay from ncs high 20 10 10 0 100 30 case 2: bustmg pin = low or rbustmg bit = 1 0**** 40*** the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: ** t8 is measured from the latest active (valid) timing among ncs, nds, a0-a2. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits *** t12 is measured from the latest active (valid) timing among ncs, a0-a2. t13 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. **** note 2: read cycle for address pointer low/high registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. note 2 is applied to an access to data register by dma transfer.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 68 smsc com20022i datasheet figure 8.9 - non-multiplexed bus, 80xx-like control signals; write cycle data hold from nwr high nwr low width nwr high width nrd to nwr low niocs16 output delay from ncs low niocs16 hold delay from ncs high a0-a2 valid data valid d0-d15 ncs t6 t1 t7 t3 t4 t2 note 2 nwr nrd t10 t8 t9 t5 note 3 t5** niocs16 valid value t11 t12 t1 t3 t5 t6 t7 t8 t9 t10 t11 t12 parameter address setup to nwr active ncs setup to wr active valid data setup to nwr high min 15 5 10 20 20 20 max 4t arb * 30*** units ns ns ns ns ns ns ns ns ns ns t4 ncs hold from nwr inactive 0 ns t2 address hold from nwr inactive 10 ns case 1: bustmg pin = high cycle time (nwr to next )** 0***** 40**** ***: ncs may become active after control becomes active, but the data setup time will now be 30 ns measured from the later of ncs falling or valid data available. the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nwr to the leading edge of the next nwr. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits **** t11 is measured from the latest active (valid) timing among ncs, a0-a2. t12 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. ***** write cycle for address pointer low register occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of the next nwr. notes 2 and 3 are applied to an access to data register by dma transfer. note 3: write cycle for address pointer low register occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of nwr. **
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 69 rev. 08-18-03 datasheet figure 8.10 - non-multiplexed bus, 80xx-like control signals; write cycle a0-a2 valid data valid d0-d15 ncs t6 t1 t7 t3 t4 t2 note 2 nwr nrd t10 t8 t9 t5 niocs16 valid value t11 t12 t5** note 3 the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: any cycle occurring after a write to address pointer low register requires a minimum of 4t arb from the trailing edge of nwr to the leading edge of the next nwr. note 2: ** write cycle for address pointer low register occurring after a write to data register requires a minimum of 5t arb from the trailing edge of nwr to the leading edge of the next nwr. notes 2 and 3 are applied to an access to data register by dma transfer. note 3: write cycle for address pointer low register occurring after a read from data register requires a minimum of 5t arb from the trailing edge of nrd to the leading edge of nwr. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits **** t11 is measured from the latest active (valid) timing among ncs, a0-a2. t12 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. ***** data hold from nwr high nwr low width nwr high width nrd to nwr low niocs16 output delay from ncs low niocs16 hold delay from ncs high t1 t3 t5 t6 t7 t8 t9 t10 t11 t12 parameter address setup to nwr active ncs setup to wr active valid data setup to nwr high min 0 0 10 65 30 20 max 4t arb * 30 units ns ns ns ns ns ns ns ns ns ns t4 ncs hold from nwr inactive 0 ns t2 address hold from nwr inactive 0 ns cycle time (nwr to next ) case 2: bustmg pin = low 0***** 40**** **
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 70 smsc com20022i datasheet figure 8.11 - non-multiplexed bus, 68xx-li ke control signals; write cycle a0-a2 valid data valid d0-d15 ncs t8 t1 t9 t3 t10 t4 t2 note 2 t5 dir t7 nds t11 t6 niocs16 valid value t12 t13 t6** parameter min max units address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds to next time )** dir hold from nds inactive valid data setup to nds high data hold from nds high nds low width nds high width niocs16 output delay from ncs low niocs16 hold delay from ncs high t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 15 10 5 0 10 4t arb * 10 30*** 10 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns case 1: bustmg pin = high 0***** 40**** the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: **note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nds to the leading edge of the next nds. ***: ncs may become active after control becomes active, but the data setup time will now be 30 ns measured from the later of ncs falling or valid data available. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits ****: t12 is measured from the latest active (valid) timing among ncs, a0-a2. t13 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. *****: write cycle for address pointer low registers occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. note 2 is applied to an access to data register by dma transfer.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 71 rev. 08-18-03 datasheet a0-a2 valid data valid d0-d15 ncs t8 t1 t9 t3 t10 t4 t2 note 2 t5 dir t7 nds t11 t6 niocs16 valid value t12 t13 t6** parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 0 0 0 0 10 4t arb * 10 30 10 65 30 ns ns ns ns ns ns ns ns ns ns ns ns ns case 2: bustmg pin = low address setup to nds active address hold from nds inactive ncs setup to nds active ncs hold from nds inactive dir setup to nds active cycle time (nds to next )** dir hold from nds inactive valid data setup to nds high data hold from nds high nds low width nds high width niocs16 output delay from ncs low niocs16 hold delay from ncs high 0***** 40**** the microcontroller typically accesses the com20022 on every other cycle. therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back com20022 cycles. note 1: **note 2: any cycle occurring after a write to the address pointer low register requires a minimum of 4t arb from the trailing edge of nds to the leading edge of the next nds. t arb is the arbitration clock period t arb is identical to t opr if slow arb = 0 * t arb is twice t opr if slow arb = 1 t opr is the period of operation clock. it depends on ckup1 and ckup0 bits **** t12 is measured from the latest active (valid) timing among ncs, a0-a2. t13 is measured from the earliest inactive (invalid) timing among ncs, a0-a2. ***** write cycle for address pointer low register occurring after an access to data register requires a minimum of 5t arb from the trailing edge of nds to the leading edge of the next nds. note 2 is applied to an access to data register by dma transfer. figure 8.12 - non-multiplexed bus, 68xx-like control signals; write cycle
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 72 smsc com20022i datasheet figure 8.13 - normal mode transmit or receive timing (these signals are to and from the hybrid) npulse2 t1 t3 t7 t8 parameter npulse1, npulse2 pulse width npulse1, npulse2 overlap rxin period rxin inactive pulse width min 100 -10 max units ns ns npulse1 t1 t6 rxin active pulse width t2 t2 npulse1, npulse2 period ns t1 t3 400 0 +10 typ rxin t6 t7 10 400 ntxen ns ns t2 t4 t5 last bit (400 ns bit time) t4 ntxen low to npulse1 low 850 950 ns t5 beginning of last bit time to ntxen high 250 350 ns 100 t8 20 ns note: use only 2.5 mbps
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 73 rev. 08-18-03 datasheet npulse1 t2 t3 rxin t10 t11 npulse2 t5 t6 (internal clk) t4 parameter min typ max units t2 t3 t4 t5 t6 t7 t8 t10 t11 t12 npulse1 pulse width npulse1 period npulse2 low to npulse1 low npulse2 high time npulse2 low time npulse2 period npulse2 high to ntxen high rxin active pulse width rxin period ns ns ns ns ns ns ns ns ns 200* 400* 100* 100* 200* 200* 400* 50 50 -25 10 t1 t7 ntxen t9 t8 last bit (400 ns bit time) t1 npulse2 high to ntxen low -25 50 ns (first rising edge on npulse2 after last bit time) t9 ntxen low to first npulse1 low** 650 750 ns t13 t12 -25 rxin inactive pulse width 20 ns t13 beginning last bit time to ntxen high** 450 ns above values are for 2.5 mbps. other data rates are shown below. 550 t dr is the data rate period *t5, t6 = t dr /4 *t2, t7, t10 = t dr /2 *t3, t11 = t dr **t9 = x t dr +/- 50 ns 7 4 **t13 = x t dr +/- 50 ns 5 4 figure 8.14 - backplane mode transmit or receive timing (these signals are to and from the differential driver or the cable)
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 74 smsc com20022i datasheet t1 t3 parameter input clock high time input clock period* min 20 50 max units ns ns xtal1 t1 t4 input clock frequency* 100 t2 input clock low time ns t3 20 typ 10 t2 20 mhz t5 frequency accuracy* -200 200 ppm note*: input clock frequency must be 20 mhz ( 100ppm or better) to use the internal clock multiplier. + - t 4 and t 5 are applied to crystal oscillaton. 4.0v 1.0v 50% of v dd figure 8.15 - ttl input timing on xtal1 pin t1 parameter nreset pulse width*** min max units nreset t1 t2 nintr high to next nintr low typ t2 nintr 5t xtl * ef = 0 ef = 1 t dr **/2 4t xtl * note*: t xtl is period of external xtal oscillation frequency. note**: t dr is period of data rate (i.e. at 2.5 mbps, t dr = 400 ns) note***: when the power is turned on, t1 is measured from stable xtal oscillation after v dd was over 4.5v. figure 8.16 - reset and interrupt timing
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 75 rev. 08-18-03 datasheet valid valid ncs nrefex dreq ndack tc nwr nrd data (d15-d0) t10 t19 t3 t2 t21 t24 t6 t20 t19 t20 t3 t7* t25 t24 t25 t5 t4 t15 t16 t11 t12 t8 t9 t14 t13 t17 t18 write low-pointer when dmaen=1 note*: t7 is measured from the latest active timing among tc, write/read. t26 t1 figure 8.17 - dma timing (intel mode 80xx)
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 76 smsc com20022i datasheet note*: t7 is measured from the latest active timing among tc, write/read. valid valid ncs nrefex dreq ndack tc dir nds data (d15-d0) t10 t19 t3 t2 t21 t24 t6 t20 t19 t20 t3 t7* t25 t24 t25 t5 t4 t15 t16 t11 t12 t8 t9 t14 t13 t17 t18 write low-pointer when dmaen=1 t22 t23 t22 t23 valid valid t26 t1 figure 8.18 - dma timing (motorola mode 68xx)
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 77 rev. 08-18-03 datasheet table 8.1 - dma timing parameter min typ max unit note t1 ndack inactive pulse width 30 ns t2 the first dreq assertion delay after writing low pointer 4 tarb 5 tarb 5tarb +40ns note 1 t3 dreq assert delay from nrefex active at programmable burst transfer mode 0 40 ns note 3 t4 dreq assertion delay from write/read inactive at non- burst transfer mode 0 40 ns note 4 t5 gttm bit =0 7txtl 8txtl +40ns note 2 dreq assertion delay from ndack inactive due to timeout of gate timer at programmable burst transfer mode gttm bit=1 15txtl 16txtl +40ns t6 dreq negation delay from write/read active 0 40 ns note 4 t7 dreq negation delay from tc and write/read active 0 40 ns note 4 t8 data access time from read active 40 ns note 4 t9 data float delay from read inactive 0 20 ns note 4 t10 nrefex active pulse width 20 ns t11 write active pulse width case 1w 20 ns note 4,5 case 2w 65 ns t12 read active pulse width case 1r 60 ns note 4,5 case 2r 100 ns t13 active pulse overlap width between tc and write/read 20 ns note 4 case1w/1r 20 ns t14 write/read inactive pulse width case2w/2r 30 ns note 4,5 t15 write cycle interval period 4tarb note 1,4 case1r 4tarb t16 read cycle interval period case2r 4tarb+3 0ns note 1,4,5 t17 data setup to write inactive 30 ns note 4 t18 data hold from write inactive 10 ns note 4 t19 ncs high setup to ndack active 20 ns t20 ncs high hold from ndack inactive 20 ns t21 dreq active setup to ndack active 20 ns t22 dir setup to nds low (motorola mode only) 10 ns t23 dir hold from nds high (motorola mode only) 10 ns t24 ndack setup to write/read active 30 ns note 4 t25 ndack hold after write/read inactive 5 ns note 4 t26 nrefex inactive time 3txtl note 2 notes: 1. tarb is the arbitration clock period. it depends on topr and slowarb bit. slowarb must set to ?1? if the data rate is over 5 mbps. (i.e. 10 mbps) tarb is topr at slowarb=0 and tarb is 2topr at slowarb=1. topr is the period of operation clock frequency. it depends on the ckup1 and ckup0 bits. 2. txtl is a period of external xtal oscillation frequency. 3. the nrefex pin must not be low while ndack is low.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 78 smsc com20022i datasheet 4. ?write? means write signal and ?read? means read signal. ?write/read? means write or read signal. at intel mode, write signal is nwr and read signal is nrd. at motorola mode, write signal is nds when dir is low and the read signal is nds when dir is high. 5. conditions of case1w, case2w, case1r and case2r are shown below; case1w : bustmg pin = high case2w : bustmg pin = low case1r : bustmg pin = high and rbustmg bit = 0 case2r : bustmg pin = low or rbustmg bit = 1
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 79 rev. 08-18-03 datasheet chapter 9 package outline figure 9.1 - com20022i 48 pin tqfp package outline table 9.1 - com20022i 48 pin tqfp package parameters min nominal max remar k a ~ ~ 1.6 overall packa g e hei g ht a1 0.05 0.10 0.15 standoff a2 1.35 1.40 1.45 bod y thickness d 8.80 9.00 9.20 x s p an d/2 4.40 4.50 4.60 1 / 2 x s p an measure from centerline d1 6.90 7.00 7.10 x bod y size e 8.80 9.00 9.10 y s p an e/2 4.40 4.50 4.60 1 / 2 y s p an measure from centerline e1 6.90 7.00 7.10 y bod y size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot len g th from centerline l1 ~ 1.00 ~ lead len g th e 0.50 basic lead pitch 0 o ~ 7 o lead foot an g le w 0.17 ~ 0.27 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ 0.0762 co p lanarit y ( assemblers ) ccc ~ ~ 0.08 co p lanarit y ( test house ) notes: 1. controlling unit: millimeter 2. tolerance on the position of the leads is 0.04 mm maximum. 3. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. 4. dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. 5. details of pin 1 identifier are optional but must be located within the zone indicated.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 80 smsc com20022i datasheet chapter 10 appendix a this appendix describes the function of the nosync and ef bits. 10.1 nosync bit the nosync bit controls whether or not the ram init ialization sequence requires the line to be idle by enabling or disabling the sync command during initialization. it is defined as follows: nosync: enable/disable sync command during initialization. nosync=0, enable (default): the line has to be idle for the ram initialization sequence to be written, nosync=1, disable: the line does not have to be idle for the ram initialization sequence to be written. the following discussion describes the function of this bit: during initialization, after the cpu writes the node id, the com20022i will write "d1"h data to address 000h and node-id to address 001h of its internal ram within 3us. these values are read as part of the diagnostic test. if the d1 and node-id initialization s equence cannot be read, the initialization routine will report it as a device diagnostic failure. these writes are controlled by a micro-program which sometimes waits if the line is active; sync is the micro-program command that causes the wait. when the micro- program waits, the initial ram write does not occur, which causes the diagnostic error. thus in this case, if the line is not idle, the initialization sequence may not be written, which will be reported as a device diagnostic failure. however, the initialization sequence and diagnostics of the com20022i should be independent of the network status. this is accomplished through some additional logic to decode the program counter, enabled by the nosync bit. when it finds that the micro- program is in the initialization routine, it disables the sync command. in this case, the initialization will not be held up by the line status. thus, by setting the nosync bit, the line does not have to be idle for the ram initialization sequence to be written. 10.2 ef bit the ef bit controls several modifications to internal operation timing and logic. it is defined as follows: ef: enable/disable the new internal operation timing and logic refinements. ef=0: (default) disable the new internal operation timing (the timing is the same as in the com20020 rev. b); ef=1: enable the new internal operation timing. the ef bit controls the following timing/logic refinements in the com20022i: a) extend interrupt disable time while the interrupt is active (nintr pin=0), the interrupt is disabled by writing the clear tx/rx interrupt and clear flag command and by reading the next-id register. this minimum disable time is changed by the data rate. for example, it is 200ns at 2.5mbps and 50ns at 10mbps. the 50ns width will be too short to for the interrupt to be seen. setting the ef bit will change the minimum disable time to always be more than 200ns even if the data rate is 10mbps . this is done by changing the clock which is supplied to the interrupt disable logic. the frequency of this clock is always 20mhz even if the data rate is 10mbps.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 81 rev. 08-18-03 datasheet b) synchronize the pre-scalar output the pre-scalar is used to change the data rate. the output clock is select ed by ckp3-1 bi ts in the setup1 register. the ckp3-1 bits are changed by writing the setup1 register from outside the cpu. it's not synchronized between the cpu and com20022i. thus, changing the ckp2-0 timing does not synchronize with the internal clocks of pre-scalar, and changing ckp2-0 may cause spike noise to appear on the output clock line. setting the ef bit will include flip-flops inserted between the setup1 register and pre-scalar for synchronizing the ckp2-0 with pre-scalar?s internal clocks. never change the ckp2-0 when the data rate is over 5 mbps. they must all be zero. c) shorten the write interval time to the command register the com20022i limits the write interval time for continuous writing to the command register. the minimum interval time is changed by the data rate. it's 100 ns at the 2.5 mbps and 1.6 s at the 156.25 kbps. this 1.6 s is very long for cpu. setting the ef bit will change the clock source from osck clock (8 times frequency of data rate) to xtal clock which is not changed by the data rate, such that the minimum interval time becomes 100 ns. d) eliminate the write prohibition period for the enable tx/rx commands the com20022i has a write prohibition period for writing the enable transmit/receive commands. this period is started by the ta or ri bit (status reg.) returning to high. this prohibition period is caused by setting the ta/ri bit with an internal pulse signal. it is 3.2 s at 156.25 kbps. this period may be a problem when using interrupt processing. the interrupt occurs when the ri bit returns to high. the cpu writes the next enable receive command to the other page immediately. in this case, the interval time between the interrupt and writing command is shorter than 3.2 s. setting the ef bit will cause the ta/ri bit to return to high upon release of the internal pulse signal for setting the ta/ri bit, instead of at the start of the pulse. this is illustra ted in figure 10.1 on the following page.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet rev. 08-18-03 page 82 smsc com20022i datasheet tx/rx completed ta/ri bit internal setting pulse nintr pin prohibition period ef=1 tx/rx completed ta/ri bit internal setting pulse nintr pin ef=0 figure 10.1 - effect of the ef bit on the ta/ri bit the ef bit also controls the resolution of the following issues from the com20020 rev b: a) network map generation tentative id is used for generating the network map, but it sometimes detects a non-existent node. every time the tentative-id register is written, the effect of the old tentative-id remains active for a while, which results in an incorrect network map. it can be avoided by a carefully coded software routine, but this requires the programmer to have deep knowledge of ho w the com20022i works. duplicate-id is mainly used for generating the network map. this has the same issue as tentative-id. a minor logic change clears al l the remaining effects of the old tent ative-id and the old duplicate-id, when the com20022i detects a write operation to tentat ive-id or node-id register. with this change, programmers can use the tentative-id or duplicate-id for generating the network map without any issues. this change is enabled/disabled by the ef bit. b) mask register reset the mask register is reset by a soft reset in the com20020 rev. a, but is not reset in rev. b. the mask register is related to the status and diagnostic register, so it should be reset by a soft reset. otherwise, every time the soft reset happens, the com20020 rev. b generates an unnecessary interrupt since the status bits ri and ta are back to one by the soft reset. this is resolved by changing the logic to reset the mask register both by the hard reset and by the soft reset. the soft reset is activated by the node-id register going to 00h or by the reset bit going to high in the configuration register. this solution is enabled/disabled by the ef bit.
10 mbps arcnet (ansi 878.1) controller with 2kx8 on-board ram datasheet smsc com20022i page 83 rev. 08-18-03 datasheet chapter 11 appendix b: example of interface circuit diagram to isa bus isa bus a en sa15- sd15- nior niow sa2- irqm niocs16 drqn ndack tc nrefres resetdr 12 12 bit comparator ls688x ng p p=q q i/o address seeting (dip 16 bit transceiver ls245x a b dir ng 3 d15-d0 nrd nwr a 2-a0 nintr niocs16 dreq ndack tc nrefex nreset ncs 16 3 schmitt-trigger open-collector 12 com2002i 5v 16 a

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